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| d a t a sh eet product speci?cation supersedes data of 2002 feb 18 2004 mar 01 integrated circuits saa7102; saa7103 digital video encoder
2004 mar 01 2 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 contents 1 features 2 general description 3 ordering information 4 quick reference data 5 block diagram 6 pinning 7 functional description 7.1 reset conditions 7.2 input formatter 7.3 rgb lut 7.4 cursor insertion 7.5 rgb y-c b -c r matrix 7.6 horizontal scaler 7.7 vertical scaler and anti-flicker filter 7.8 fifo 7.9 border generator 7.10 oscillator and discrete time oscillator (dto) 7.11 low-pass clock generation circuit (cgc) 7.12 encoder 7.13 rgb processor 7.14 triple dac 7.15 timing generator 7.16 i 2 c-bus interface 7.17 programming the saa7102; saa7103 7.18 input levels and formats 7.19 bit allocation map 7.20 i 2 c-bus format 7.21 slave receiver 7.22 slave transmitter 8 boundary scan test 8.1 initialization of boundary scan circuit 8.2 device identification codes 9 limiting values 10 thermal characteristics 11 characteristics 11.1 teletext timing 12 application information 12.1 analog output voltages 12.2 suggestions for a board layout 13 package outlines 14 soldering 14.1 introduction to soldering surface mount packages 14.2 reflow soldering 14.3 wave soldering 14.4 manual soldering 14.5 suitability of surface mount ic packages for wave and reflow soldering methods 15 data sheet status 16 definitions 17 disclaimers 18 purchase of philips i 2 c components 2004 mar 01 3 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 1 features digital pal/ntsc encoder with integrated high quality scaler and anti-flicker filter for tv output from a pc 27 mhz crystal-stable subcarrier generation maximum graphics pixel clock 45 mhz at double edged clocking, synthesized on-chip or from external source up to 800 600 graphics data at 60 hz or 50 hz with programmable underscan range three digital-to-analog converters (dacs) at 27 mhz sample rate for cvbs (blue, c b ), vbs (green, cvbs) and c (red, c r ) (signals in parenthesis are optional); all at 10-bit resolution non-interlaced c b -y-c r or rgb input at maximum 4:4:4 sampling downscaling from 1 : 1 to 1 : 2 and up to 20% upscaling optional interlaced c b -y-c r input digital versatile disk (dvd) optional non-interlaced rgb output to drive second vga monitor (bypass mode, maximum 45 mhz) 3 256 bytes rgb look-up table (lut) support for hardware cursor programmable border colour of underscan area on-chip 27 mhz crystal oscillator (3rd-harmonic or fundamental 27 mhz crystal) fast i 2 c-bus control port (400 khz) encoder can be master or slave programmable horizontal and vertical input synchronization phase programmable horizontal sync output phase internal colour bar generator (cbg) optional support of various vertical blanking interval (vbi) data insertion macrovision ? (1) pay-per-view copy protection system rev. 7.01 and rev. 6.1 as option; this applies to the saa7102 only. the device is protected by usa patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. use of the macrovision anti-copy process in the device is licensed for non-commercial home use only. reverse engineering or disassembly is prohibited. please contact your nearest philips semiconductors sales office for more information. power-save modes joint test action group (jtag) boundary scan test monolithic cmos 3.3 v device, 5 v tolerant i/os qfp44 and bga156 packages same footprint as saa7108e; saa7109e. 2 general description the saa7102; saa7103 is used to encode pc graphics data at maximum 800 600 resolution to pal (50 hz) or ntsc (60 hz) video signals. a programmable scaler and interlacer ensures properly sized and flicker-free tv display as cvbs or s-video output. alternatively, the three digital-to-analog converters (dacs) can output rgb signals together with a ttl composite sync to feed scart connectors. when the scaler/interlacer is bypassed, a second vga monitor can be connected to the rgb outputs and separate h and v-syncs as well, thereby serving as an auxiliary monitor at maximum 800 600 resolution/60 hz (pixclk < 45 mhz). the device includes a sync/clock generator and on-chip dacs. (1) macrovision ? is a trademark of the macrovision corporation. 2004 mar 01 4 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 3 ordering information 4 quick reference data type number package name description version saa7102e bga156 plastic ball grid array package; 156 balls; body 15 15 1.15 mm sot472-1 saa7103e saa7102h qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 saa7103h symbol parameter min. typ. max. unit v dda analog supply voltage 3.15 3.3 3.45 v v ddd digital supply voltage 3.0 3.3 3.6 v i dda analog supply current 1 110 140 ma i ddd digital supply current 1 70 90 ma v i input signal voltage levels ttl compatible v o(p-p) analog cvbs output signal voltage for a 100/100 colour bar at 75/2 w load (peak-to-peak value) - 1.23 - v r l load resistance - 37.5 -w ile lf(dac) low frequency integral linearity error of dacs -- 3 lsb dle lf(dac) low frequency differential linearity error of dacs -- 1 lsb t amb ambient temperature 0 - 70 c 2004 mar 01 5 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 5 block diagram vertical scaler and anti-flicker filter fifo horizontal scaler decimator 4 : 4 : 4 to 4 : 2 : 2 (or bypass) triple dac blue_cb_cvbs green_vbs_cvbs red_cr_c 30 28 27 hsm_csync 26 vsm 25 video encoder border generator cursor insertion rgb to y-c b -c r matrix (or bypass) rgb lut (or bypass) i 2 c-bus control oscillator/ dto timing generator 13 34 35 23 fsvgc vsvgc xtal 27 mhz ttx_sres xtali hsvgc cbo ttxrq_xclko2 14 21 12 sda scl 11 5 22 24 cgc low-pass input formatter v ddd1 10 4 to 1, 44 to 41, 16 to 19 v ssd1 9 15 pd11 to pd0 pixclki 20 pixclko v ddd2 40 v ssd2 39 v dda2 36 v dda1 29 v ssa1 33 dump 32 rset 31 tdi 38 trst 37 tck 8 tms 6 tdo 7 mhb963 saa7102h saa7103h reset fig.1 block diagram. 2004 mar 01 6 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 6 pinning symbol pin pin type (1) description bga156 qfp44 pd8 b2 1 i see tables 25 to 30 for pin assignment pd9 b1 2 i see tables 25 to 30 for pin assignment pd10 c2 3 i see tables 25 to 30 for pin assignment pd11 c1 4 i see tables 25 to 30 for pin assignment reset d2 5 i reset input; active low tms d3 6 i test mode select input for boundary scan test (bst); note 2 tdo d1 7 o test data output for bst; note 2 tck e1 8 i test clock input for bst; note 2 v ssd1 e4 9 s digital ground 1 (peripheral cells) v ddd1 f4 10 s digital supply voltage 1 (3.3 v for peripheral cells) scl e2 11 i i 2 c-bus serial clock input sda g2 12 i/o i 2 c-bus serial data input/output fsvgc g1 13 i/o frame synchronization output to video graphics controller (vgc) (optional input); note 3 vsvgc f1 14 i/o vertical synchronization output to vgc (optional input); note 3 pixclki f2 15 i pixel clock input (looped through) pd3 f3 16 i msb - 4 with c b -y-c r 4 : 2 : 2; see tables 25 to 30 for pin assignment pd2 h1 17 i msb - 5 with c b -y-c r 4 : 2 : 2; see tables 25 to 30 for pin assignment pd1 h2 18 i msb - 6 with c b -y-c r 4 : 2 : 2; see tables 25 to 30 for pin assignment pd0 h3 19 i msb - 7 with c b -y-c r 4 : 2 : 2; see tables 25 to 30 for pin assignment pixclko g4 20 o pixel clock output to vgc cbo g3 21 o composite blanking output to vgc; active low; note 3 hsvgc e3 22 i/o horizontal synchronization output to vgc (optional input); note 3 ttx_sres c3 23 i teletext input or sync reset input ttxrq_xclko2 c4 24 o teletext request output or 13.5 mhz clock output of the crystal oscillator; note 3 vsm d7 25 o vertical synchronization output to monitor (non-interlaced auxiliary rgb) hsm_csync d8 26 o horizontal synchronization output to monitor (non-interlaced auxiliary rgb) or composite sync for rgb-scart red_cr_c c8 27 o analog output of red or c r or c signal green_vbs_cvbs c7 28 o analog output of green or vbs or cvbs signal v dda1 a10, b9, c9, d9 29 s analog supply voltage 1 (3.3 v for dacs) blue_cb_cvbs c6 30 o analog output of blue or c b or cvbs signal 2004 mar 01 7 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 notes 1. pin type: i = input, o = output, s = supply. 2. in accordance with the ieee1149.1 standard the pins tdi, tms, tck and trst are input pins with an internal pull-up resistor and tdo is a 3-state output pin. 3. pins fsvgc, vsvfc, cbo, hsvgc and ttxrq_xclko2 are used for bootstrapping; see section 7.1 4. for board design without boundary scan implementation connect trst to ground. 5. this pin provides easy initialization of the boundary scan test (bst) circuit. trst can be used to force the test access port (tap) controller to the test_logic_reset state (normal operation) at once. rset a9 31 o dac reference pin; connected via 1 k w resistor to analog ground (do not use capacitor in parallel with 1 k w resistor) dump a7, b7 32 o dac reference pin; connected via 12 w resistor to analog ground v ssa1 a8, b8 33 s analog ground 1 xtalo a6 34 o crystal oscillator output xtali a5 35 i crystal oscillator input v dda2 b6, d6 36 s analog supply voltage 2 (3.3 v for dacs and oscillator) trst a4 37 i test reset input for bst; active low; notes 2, 4 and 5 tdi b5 38 i test data input for bst; note 2 v ssd2 c5, d5 39 s digital ground 2 v ddd2 d4 40 s digital supply voltage 2 (3.3 v for core) pd4 a3 41 i msb - 3 with c b -y-c r 4 : 2 : 2; see tables 25 to 30 for pin assignment pd5 b3 42 i msb - 2 with c b -y-c r 4 : 2 : 2; see tables 25 to 30 for pin assignment pd6 b4 43 i msb - 1 with c b -y-c r 4 : 2 : 2; see tables 25 to 30 for pin assignment pd7 a2 44 i msb with c b -y-c r 4 : 2 : 2; see tables 25 to 30 for pin assignment symbol pin pin type (1) description bga156 qfp44 2004 mar 01 8 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 1 pin assignment saa7102e; saa7103e (top view) 1 2 3 4 5 6 7 8 9 1011121314 a pd7 pd4 trst xtali xtalo dump v ssa1 rset v dda1 b pd9 pd8 pd5 pd6 tdi v dda2 dump v ssa1 v dda1 c pd11 pd10 ttx_ sres ttxrq_ xclko2 v ssd2 blue_ cb_ cvbs green_ vbs_ cvbs red_ cr_ c v dda1 d tdo reset tms v ddd2 v ssd2 v dda2 vsm hsm_ csync v dda1 e tck scl hsvgc v ssd1 f vsvgcpixclki pd3 v ddd1 g fsvgc sda cbo pixclko h pd2 pd1 pd0 j k l m n p 2004 mar 01 9 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 handbook, halfpage 1 a b c d e f g h j k l m n p 234567891011121314 mhb907 saa7102e saa7103e fig.2 pin configuration (saa7102e; saa7103e). handbook, full pagewidth saa7102h saa7103h mhb908 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 pd7 pd6 pd5 pd4 v ddd2 v ssd2 tdi trst v dda2 xtali xtalo sda fsvgc vsvgc pixclki pd3 pd2 pd1 pd0 pixclko cbo hsvgc pd8 pd9 pd10 pd11 tms tdo tck v ssd1 v ddd1 scl v ssa1 dump rset blue_cb_cvbs v dda1 green_vbs_cvbs red_cr_c hsm_csync vsm ttxrq_xclko2 ttx_sres reset fig.3 pin configuration (saa7102h; saa7103h). 2004 mar 01 10 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 7 functional description the digital video encoder encodes digital luminance and colour difference signals (c b -y-c r ) or digital rgb signals into analog cvbs, s-video and, optionally, rgb or c r -y-c b signals. ntsc m, pal b/g and sub-standards are supported. the saa7102; saa7103 can be directly connected to a pc video graphics controller with a maximum resolution of 800 600 at a 50 or 60 hz frame rate. a programmable scaler scales the computer graphics picture so that it will fit into a standard tv screen with an adjustable underscan area. non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness. besides the most common 16-bit 4 :2:2 c b -y-c r input format (using 8 pins with double edge clocking), other c b -y-c r and rgb formats are also supported; see tables 25 to 30. a complete 3 256 bytes look-up table (lut), which can be used, for example, as a separate gamma corrector, is located in the rgb domain; it can be loaded either through the video input port pd (pixel data) or via the i 2 c-bus. the saa7102; saa7103 supports a 32 32 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the i 2 c-bus. it is also possible to encode interlaced 4 :2:2 video signals such as pc-dvd; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. besides the applications for video output, the saa7102; saa7103 can also be used for generating a kind of auxiliary vga output, when the rgb non-interlaced input signal is fed to the dacs. this may be of interest for example, when the graphics controller provides a second graphics window at its video output port. the basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 mhz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 :2:2 bandwidth in the luminance/colour difference domain. luminance and chrominance signals are filtered in accordance with the standard requirements of rs-170-a and itu-r bt.470-3 . for ease of analog post filtering the signals are twice oversampled to 27 mhz before digital-to-analog conversion. the total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in figs 4 to 9. all three dacs are realized with full 10-bit resolution. the c r -y-c b to rgb dematrix can be bypassed (optionally) in order to provide the upsampled c r -y-c b input signals. the 8-bit multiplexed c b -y-c r formats are itu-r bt.656 (d1 format) compatible, but the sav and eav codes can be decoded optionally, when the device is operated in slave mode. for assignment of the input data to the rising or falling clock edge see tables 25 to 30. in order to display interlaced rgb signals through a euro-connector tv set, a separate digital composite sync signal (pin hsm_csync) can be generated; it can be advanced up to 31 periods of the 27 mhz crystal clock in order to be adapted to the rgb processing of a tv set. the saa7102; saa7103 synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. wide screen signalling data can be loaded via the i 2 c-bus and is inserted into line 23 for standards using a 50 hz field rate. vps data for program dependent automatic start and stop of such featured vcrs is loadable via the i 2 c-bus. the ic also contains closed caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 mhz clock rate (see fig.14). it is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting). a number of possibilities are provided for setting different video parameters such as: black and blanking level control colour subcarrier frequency variable burst amplitude etc. 2004 mar 01 11 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 7.1 reset conditions to activate the reset a pulse at least of 2 crystal clocks duration is required. during reset ( reset = low) plus an extra 32 crystal clock periods, fsvgc, vsvgc, cbo, hsvgc and ttx_sres are set to input mode and hsm_csync and vsm are set to 3-state. a reset also forces the i 2 c-bus interface to abort any running bus transfer and sets it into receive condition. after reset, the state of the i/os and other functions is defined by the strapping pins until an i 2 c-bus access redefines the corresponding registers; see table 2. table 2 strapping pins 7.2 input formatter the input formatter converts all accepted pd input data formats, either rgb or y-c b -c r , to a common internal rgb or y-c b -c r data stream. when double-edge clocking is used, the data is internally split into portions ppd1 and ppd2. the clock edge assignment must be set according to the i 2 c-bus control bits edge1 and edge2 for correct operation. if y-c b -c r is being applied as a 27 mbyte/s data stream, the output of the input formatter can be used directly to feed the video encoder block. 7.3 rgb lut the three 256 byte rams of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for rgb signals. in the event that the indexed colour data is applied, the rams are addressed in parallel. the luts can either be loaded by an i 2 c-bus write access or can be part of the pixel data input through the pd port. in the latter case, 256 3 bytes for the r, g and b lut are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. the first 3 bytes represent the first rgb lut data, and so on. 7.4 cursor insertion a32 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an i 2 c-bus write access to specific registers or in the pixel data input through the pd port. in the latter case, the 256 bytes defining the cursor bit map (2 bits per pixel) are expected immediately following the last rgb lut data in the line preceding the first active line. the cursor bit map is set up as follows: each pixel occupies 2 bits. the meaning of these bits depends on the cmode i 2 c-bus register as described in table 5. transparent means that the input pixels are passed through, the cursor colours can be programmed in separate registers. the bit map is stored with 4 pixels per byte, aligned to the least significant bit. so the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. the first index is the column, followed by the row; index 0,0 is the upper left corner. table 3 layout of a byte in the cursor bit map for each direction, there are 2 registers controlling the position of the cursor, one controls the position of the hot spot, the other register controls the insertion position. the hot spot is the tip of the pointer arrow. pin tied preset fsvgc low ntsc m encoding, pixclk ?ts to 640 480 graphics input high pal b/g encoding, pixclk ?ts to 640 480 graphics input vsvgc low 4:2:2 y-c b -c r graphics input (format 0) high 4:4:4 rgb graphics input (format 3) cbo low input demultiplex phase: lsb=low high input demultiplex phase: lsb = high hsvgc low input demultiplex phase: msb = low high input demultiplex phase: msb = high ttxrq_xclko2 low slave (fsvgc, vsvgc and hsvgc are inputs, internal colour bar is active) high master (fsvgc, vsvgc and hsvgc are outputs) d7 d6 d5 d4 d3 d2 d1 d0 pixel n + 3 pixel n + 2 pixel n + 1 pixel n d1 d0 d1 d0 d1 d0 d1 d0 2004 mar 01 12 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 it can have any position in the bit map. the actual position register describe the co-ordinates of the hot spot. again 0,0 is the upper left corner. while it is not possible to move the hot spot beyond the left respectively upper screen border this is perfectly legal for the right respectively lower border. it should be noted that the cursor position is described relative to the input resolution. table 4 cursor bit map table 5 cursor modes 7.5 rgb y-c b -c r matrix rgb input signals to be encoded to pal or ntsc are converted to the y-c b -c r colour space in this block. the colour difference signals are fed through low-pass filters and formatted to a itu-r bt.601 like 4 : 2 : 2 data stream for further processing. the matrix and formatting blocks can be bypassed for y-c b -c r graphics input. when the auxiliary vga mode is selected, the output of the cursor insertion block is immediately directed to the triple dac. 7.6 horizontal scaler the high quality horizontal scaler operates on the 4 : 2 : 2 data stream. its control engines compensate the colour phase offset automatically. the scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. each input pixel is a programmable fraction of the current output pixel (xinc/4096). a special case is xinc = 0, this sets the scaling factor to 1. if the saa7102; saa7103 input data is in accordance with itu-r bt.656 , the scaler enters another mode. in this event, xinc needs to be set to 2048 for a scaling factor of 1. with higher values, upscaling will occur. the phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. small fifos rearrange a 4 : 2 : 2 data stream at the scaler output. 7.7 vertical scaler and anti-?icker ?lter the functions scaling, anti-flicker filter (aff) and re-interlacing are implemented in the vertical scaler. besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering. the circuit generates the interlaced output fields by scaling down the input frames with different offsets for odd and even fields. increasing the yskip setting reduces the anti-flicker function. a yskip value of 4095 switches it off; see table 95. the programming is similar to the horizontal scaler. for the re-interlacing, the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. yinc = 0 sets the scaling factor to 1; yiwgto and yiwgte must not be 0. due to the re-interlacing, the circuit can perform upscaling. the maximum factor depends on the setting of the anti-flicker function and can be derived from the formulae given in section 7.17. byte d7 d6 d5 d4 d3 d2 d1 d0 0row0 column 3 row 0 column 2 row 0 column 1 row 0 column 0 1row0 column 7 row 0 column 6 row 0 column 5 row 0 column 4 2row0 column 11 row 0 column 10 row 0 column 9 row 0 column 8 ... ... ... ... ... 6row0 column 27 row 0 column 26 row 0 column 25 row 0 column 24 7row0 column 31 row 0 column 30 row 0 column 29 row 0 column 28 ... ... ... ... ... 254 row 31 column 27 row 31 column 26 row 31 column 25 row 31 column 24 255 row 31 column 31 row 31 column 30 row 31 column 29 row 31 column 28 cursor pattern cursor mode cmode = 0 cmode = 1 00 second cursor colour second cursor colour 01 ?rst cursor colour ?rst cursor colour 10 transparent transparent 11 inverted input auxiliary cursor colour 2004 mar 01 13 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 7.8 fifo the fifo acts as a buffer to translate from the pixclk clock domain to the xtal clock domain. the write clock is pixclk and the read clock is xtal. an underflow or overflow condition can be detected via the i 2 c-bus read access. in order to avoid underflows and overflows, it is essential that the frequency of the synthesized pixclk matches to the input graphics resolution and the desired scaling factor. it is suggested to refer to tables 6 to 23 for some representative combinations. 7.9 border generator when the graphics picture is to be displayed as interlaced pal, ntsc, s-video or rgb on a tv screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a tv set. the desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true colour tint. 7.10 oscillator and discrete time oscillator (dto) the master clock generation is realized as a 27 mhz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal. the crystal clock supplies the dto of the pixel clock synthesizer, the video encoder and the i 2 c-bus control block. it also usually supplies the triple dac, with the exception of the auxiliary vga mode, where the triple dac is clocked by the pixel clock (pixclk). the dto can be programmed to synthesize all relevant pixel clock frequencies between circa 18 and 44 mhz. 7.11 low-pass clock generation circuit (cgc) this block reduces the phase jitter of the synthesized pixel clock. it works as a tracking filter for all relevant synthesized pixel clock frequencies. 7.12 encoder 7.12.1 v ideo path the encoder generates luminance and colour subcarrier output signals from the y, c b and c r baseband signals, which are suitable for use as cvbs or separate y and c signals. input to the encoder, at 27 mhz clock (e.g. dvd), is either originated from computer graphics at pixel clock, fed through the fifo and border generator, or a itu-r bt.656 style signal. luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). a blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes. other manipulations used for the macrovision anti-taping process, such as additional insertion of agc super-white pulses (programmable in height), are supported by the saa7102 only. to enable easy analog post filtering, luminance is interpolated from a 13.5 mhz data rate to a 27 mhz data rate, thereby providing luminance in a 10-bit resolution. the transfer characteristics of the luminance interpolation filter are illustrated in figs 6 and 7. appropriate transients at start/end of active video and for synchronization pulses are ensured. chrominance is modified in gain (programmable separately for c b and c r ), and a standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 mhz data rate to a 27 mhz data rate. one of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be used for the y and c output. the transfer characteristics of the chrominance interpolation filter are illustrated in figs 4 and 5. the amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. after the succeeding quadrature modulator, colour is provided on the subcarrier in 10-bit resolution. the numeric ratio between the y and c outputs is in accordance with the standards. 7.12.2 t eletext insertion and encoding ( not simultaneously with real - time control ) pin ttx_sres receives a wst or nabts teletext bitstream sampled at the crystal clock. at each rising edge of the output signal (ttxrq) a single teletext bit has to be provided after a programmable delay at input pin ttx_sres. 2004 mar 01 14 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. ttxrq_xclko2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. the internal insertion window for text is set to 360 (pal wst), 296 (ntsc wst) or 288 (nabts) teletext bits including clock run-in bits. the protocol and timing are illustrated in fig.14. alternatively, this pin can be provided with a buffered crystal clock (xclk) of 13.5 mhz. 7.12.3 v ideo p rogramming s ystem (vps) encoding five bytes of vps information can be loaded via the i 2 c-bus and will be encoded in the appropriate format into line 16. 7.12.4 c losed c aption encoder using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. the actual line number in which data is to be encoded, can be modified in a certain range. the data clock frequency is in accordance with the definition for ntsc m standard 32 times horizontal line frequency. data low at the output of the dacs corresponds to 0 ire, data high at the output of the dacs corresponds to approximately 50 ire. it is also possible to encode closed caption data for 50 hz field frequencies at 32 times the horizontal line frequency. 7.12.5 a nti - taping (saa7102 only ) for more information contact your nearest philips semiconductors sales office. 7.13 rgb processor this block contains a dematrix in order to produce red, green and blue signals to be fed to a scart plug. before y, c b and c r signals are de-matrixed, individual gain adjustment for y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. the transfer curves of luminance and colour difference components of rgb are illustrated in figs 8 and 9. 7.14 triple dac both y and c signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. y and c signals are also combined into a 10-bit cvbs signal. the cvbs output signal occurs with the same processing delay as the y, c and optional rgb or c r -y-c b outputs. absolute amplitude at the input of the dac for cvbs is reduced by 15 16 with respect to y and c dacs to make maximum use of the conversion ranges. red, green and blue signals are also converted from digital-to-analog, each providing a 10-bit resolution. the reference currents of all three dacs can be adjusted individually in order to adapt for different output signals. in addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. alternatively, all currents can be switched off to reduce power dissipation. all three outputs can be used to sense for an external load (usually 75 w ) during a pre-defined output. a flag in the i 2 c-bus status byte reflects whether a load is applied or not. if the saa7102; saa7103 is required to drive a second (auxiliary) vga monitor, the dacs receive the signal directly from the cursor insertion block. in this event, the dacs are clocked at the incoming pixclki instead of the 27 mhz crystal clock used in the video encoder. 7.15 timing generator the synchronization of the saa7102; saa7103 is able to operate in two modes; slave mode and master mode. in slave mode, the circuit accepts sync pulses on the bidirectional fsvgc (frame sync), vsvgc (vertical sync) and hsvgc (horizontal sync) pins: the polarities of the signals can be programmed. the frame sync signal is only necessary when the input signal is interlaced, in other cases it may be omitted. if the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the hfs and vfs bits. hsvgc and vsvgc are not necessary in this case, so it is possible to switch the pins to output mode. alternatively, the device can be triggered by auxiliary codes in a itu-r bt.656 data stream via pd7 to pd0. 2004 mar 01 15 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 only vertical frequencies of 50 and 60 hz are allowed with the saa7102; saa7103. in slave mode, it is not possible to lock the encoders colour carrier to the line frequency with the phres bits. in the (more common) master mode, the time base of the circuit is continuously free-running. the ic can output a frame sync at pin fsvgc, a vertical sync at pin vsvgc, a horizontal sync at pin hsvgc and a composite blanking signal at pin cbo. all of these signals are defined in the pixclk domain. the duration of hsvgc and vsvgc are fixed, they are 64 clocks for hsvgc and 1 line for vsvgc. the leading slopes are in phase and the polarities can be programmed. the input line length can be programmed. the field length is always derived from the field length of the encoder and the pixel clock frequency that is being used. cbo acts as a data request signal. the circuit accepts input data at a programmable number of clocks after cbo goes active. this signal is programmable and it is possible to adjust the following (see figs 12 and 13): the horizontal offset the length of the active part of the line the distance from active start to first expected data the vertical offset separately for odd and even fields the number of lines per input field. in most cases, the vertical offsets for odd and even fields are equal. if they are not, then the even field will start later. the saa7102; saa7103 will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets. as stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. the timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. the additional request pulses will be suppressed with lutl set to logic 0; see table 105. the other vertical timings do not change in this case, so the first active line can be number 2, counted from 0. 7.16 i 2 c-bus interface the i 2 c-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. it uses 8-bit subaddressing with an auto-increment function. all registers are write and read, except two read only status bytes. the register bit map consists of an rgb look-up table (lut), a cursor bit map and control registers. the lut contains three banks of 256 bytes, where each rgb triplet is assigned to one address. thus a write access needs the lut address and three data bytes following subaddress ffh. for further write access auto-incrementing of the lut address is performed. the cursor bit map access is similar to the lut access but contains only a single byte per address. the i 2 c-bus slave address is defined as 88h. 7.17 programming the saa7102; saa7103 in order to program the saa7102; saa7103 it is first necessary to determine the input and output field timings. the timings are controlled by decoding binary counters that index the position in the current line and field respectively. in both cases, 0 means the start of the sync pulse. at 60 hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 hz, the index is 284, 702 pixels can be visible. some variables are defined below: inpix: the number of active pixels per input line inppl: the length of the entire input line in pixel clocks inlin: the number of active lines per input field/frame tpclk: the pixel clock period outpix: the number of active pixels per output line outlin: the number of active lines per output field txclk: the encoder clock period (37.037 ns). the output lines should be centred on the screen. it should be noted that the encoder has 2 clocks per pixel; see table 72. adwhs = 256 + 710 - outpix (60 hz); adwhs = 284 + 702 - outpix (50 hz); adwhe = adwhs + outpix 2 (all frequencies) for vertical, the procedure is the same. at 60 hz, the first line with video information is number 19, 240 lines can be active. for 50 hz, the numbers are 23 and 287; see table 78. (60 hz); (50 hz); lal = fal + outlin (all frequencies) fal 19 240 outlin C 2 --------------------------------- + = fal 23 287 outlin C 2 --------------------------------- + = 2004 mar 01 16 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 most tv sets use overscan, and not all pixels respectively lines are visible. there is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. a reasonable underscan factor is 10%, giving approximately 640 output pixels per line. the total number of pixel clocks per line and the input horizontal offset need to be chosen next. the only constraint is that the horizontal blanking has at least 10 clock pulses. the required pixel clock frequency can be determined in the following way: due to the limited internal fifo size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. the scaler also has to process the first and last border lines for the anti-flicker function. thus: (60 hz) (50 hz) and for the pixel clock generator (all frequencies); see table 81. the input vertical offset can be taken from the assumption that the scaler should just have finished writing the first line when the encoder starts reading it: (60 hz) (50 hz) in most cases the vertical offsets will be the same for odd and even fields. the results should be rounded down. once the timings are known the scaler can be programmed. xofs can be chosen arbitrarily, the condition being that xofs + xpix hlen is fulfilled. values given by the vesa display timings are preferred. hlen = inppl - 1 xinc needs to be rounded up, it needs to be set to 0 for a scaling factor of 1. ypix = inlin yskip defines the anti-flicker function. 0 means maximum flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. when yinc = 0 it sets the scaler to scaling factor 1. the initial weighting factors must not be set to 0 in this case. yiwgte may go negative. in this event, yinc should be added and yofse incremented. this can be repeated as often as necessary to make yiwgte positive. due to the limited amount of memory it is not possible to get valid vertical scaler settings only from the formulae above. in some cases it is necessary to adjust the vertical offsets or the scaler increment to get valid settings. tables 6 to 23 show verified settings. they are organised in the following way: the tables are separate for the standard to be encoded, the input resolution and three different anti-flicker filter settings. each table contains 5 vertical sizes with 5 different offsets. they are intended to be selected according to the current tv set. the corresponding horizontal resolutions of 640 pixels give proper aspect ratios. they can be adjusted according to the formulae above. the next line gives a minimum size intended to fit on the screen under all circumstances. the corresponding horizontal resolution is 620 pixels. overscan is only possible with an input resolution of 800 600 pixels. where possible, the corresponding settings are given on the last lines of the tables. tpclk 262.5 1716 txclk inppl integer inlin 2 + outlin ---------------------- 262.5 ? ?? ---------------------------------------------------------------------------------------- = tpclk 312.5 1728 txclk inppl integer inlin 2 + outlin ---------------------- 312.5 ? ?? ---------------------------------------------------------------------------------------- = pcl txclk tpclk -------------- - 2 21 = yofs fal 1716 txclk inppl tpclk --------------------------------------------------- - 2 C = yofs fal 1728 txclk inppl tpclk --------------------------------------------------- - 2 C = xpix inpix 2 ------------ - = xinc outpix inpix ----------------- - 4096 = yinc outlin inlin 2 + ---------------------- 1 yskip 4095 ----------------- + ? ?? 4096 = yiwgto yinc 2 ------------- - 2048 + = yiwgte yinc yskip C 2 ------------------------------------- - = 2004 mar 01 17 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 7.18 input levels and formats the saa7102; saa7103 accepts digital y, c b ,c r or rgb data with levels (digital codes) in accordance with itu-r bt.601 ; see table 24. for c and cvbs outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 ire set-up or without set-up. the rgb, respectively c r -y-c b path features an individual gain setting for luminance (gy) and colour difference signals (gcd). reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. table 6 y scaler programming at ntsc, input frame size: 640 400, full anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 212 - 4 29 241 1851099 2163 0 52 52 3128 1080 212 - 2 31 243 1851099 2163 0 56 56 3128 1080 212 0 33 245 1851099 2163 0 60 60 3128 1080 212 2 35 247 1851099 2163 0 63 63 3128 1080 212 4 37 249 1851099 2163 0 67 67 3128 1080 214 - 4 28 242 1836201 2181 0 50 50 3138 1090 214 - 2 30 244 1836201 2181 0 54 54 3138 1090 214 0 32 246 1836201 2181 0 57 57 3138 1090 214 2 34 248 1836201 2181 0 61 61 3138 1090 214 4 36 250 1836201 2181 0 65 65 3138 1090 216 - 4 27 243 1817578 2202 0 47 47 3148 1100 216 - 2 29 245 1817578 2202 0 51 51 3148 1100 216 0 31 247 1817578 2202 0 55 55 3148 1100 216 2 33 249 1817578 2202 0 58 58 3148 1100 216 4 35 251 1817578 2202 0 62 62 3148 1100 218 - 4 26 244 1802680 2222 0 45 45 3158 1110 218 - 2 28 246 1802680 2222 0 49 49 3158 1110 218 0 30 248 1802680 2222 0 53 53 3158 1110 218 2 32 250 1802680 2222 0 56 56 3158 1110 218 4 34 252 1802680 2222 0 60 60 3158 1110 220 - 4 25 245 1784057 2245 0 43 43 3168 1120 220 - 2 27 247 1784057 2245 0 46 46 3168 1120 220 0 29 249 1784057 2245 0 50 50 3168 1120 220 2 31 251 1784057 2245 0 54 54 3168 1120 220 4 33 253 1784057 2245 0 57 57 3168 1120 overscan (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 204 0 37 241 1925590 2079 0 70 70 3087 1039 2004 mar 01 18 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 7 y scaler programming at ntsc, input frame size: 640 400, half anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 212 - 4 29 241 1851099 3123 1820 52 52 3668 596 212 - 2 31 243 1851099 3123 1820 56 56 3668 596 212 0 33 245 1851099 3123 1820 60 60 3668 596 212 2 35 247 1851099 3123 1820 64 64 3668 596 212 4 37 249 1851099 3123 1820 67 67 3668 596 214 - 4 28 242 1836201 3135 1790 50 50 3683 611 214 - 2 30 244 1836201 3135 1790 54 54 3683 611 214 0 32 246 1836201 3135 1790 58 58 3683 611 214 2 34 248 1836201 3135 1790 61 61 3683 611 214 4 36 250 1836201 3135 1790 65 65 3683 611 216 - 4 27 243 1817578 3145 1750 48 48 3698 626 216 - 2 29 245 1817578 3145 1750 51 51 3698 626 216 0 31 247 1817578 3145 1750 55 55 3698 626 216 2 33 249 1817578 3145 1750 59 59 3698 626 216 4 35 251 1817578 3145 1750 63 63 3698 626 218 - 4 26 244 1802680 3155 1720 45 45 3714 642 218 - 2 28 246 1802680 3155 1720 49 49 3714 642 218 0 30 248 1802680 3155 1720 53 53 3714 642 218 2 32 250 1802680 3155 1720 56 56 3714 642 218 4 34 252 1802680 3155 1720 60 60 3714 642 220 - 4 25 245 1784057 3165 1680 43 43 3729 657 220 - 2 27 247 1784057 3165 1680 47 47 3729 657 220 0 29 249 1784057 3165 1680 50 50 3729 657 220 2 31 251 1784057 3165 1680 54 54 3729 657 220 4 33 253 1784057 3165 1680 58 58 3729 657 full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 204 0 37 241 1925590 3087 1980 70 70 3589 551 2004 mar 01 19 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 8 y scaler programming at ntsc, input frame size: 640 400, no anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 212 - 4 29 241 1851099 4094 3655 52 52 4092 216 212 - 2 31 243 1851099 4094 3655 56 56 4092 216 212 0 33 245 1851099 4094 3655 60 60 4092 216 212 2 35 247 1851099 4094 3655 64 64 4092 216 212 4 37 249 1851099 4094 3655 68 68 4092 216 214 - 4 28 242 1836201 4090 3580 50 50 4091 253 214 - 2 30 244 1836201 4090 3580 54 54 4091 253 214 0 32 246 1836201 4090 3580 58 58 4091 253 214 2 34 248 1836201 4088 3580 61 61 4091 253 214 4 36 250 1836201 4088 3580 65 65 4091 253 216 - 4 27 243 1817578 4093 3510 48 48 4091 288 216 - 2 29 245 1817578 4093 3510 52 52 4091 288 216 0 31 247 1817578 4093 3510 55 55 4091 288 216 2 33 249 1817578 4093 3510 59 59 4091 288 216 4 35 251 1817578 4093 3510 63 63 4091 288 218 - 4 26 244 1802680 4092 3445 46 46 4092 322 218 - 2 28 246 1802680 4092 3445 49 49 4092 322 218 0 30 248 1802680 4092 3445 53 53 4092 322 218 2 32 250 1802680 4092 3445 57 57 4092 322 218 4 34 252 1802680 4092 3445 60 60 4092 322 220 - 4 25 245 1784057 4090 3370 43 43 4091 358 220 - 2 27 247 1784057 4090 3370 47 47 4091 358 220 0 29 249 1784057 4090 3370 50 50 4091 358 220 2 31 251 1784057 4090 3370 54 54 4091 358 220 4 33 253 1784057 4090 3370 58 58 4091 358 full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 204 0 37 241 1925590 4087 3950 70 70 4089 66 2004 mar 01 20 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 9 y scaler programming at ntsc, input frame size: 640 480, full anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 212 - 4 29 241 2219829 1804 0 63 63 2948 900 212 - 2 31 243 2219829 1804 0 67 67 2948 900 212 0 33 245 2219829 1804 0 72 72 2948 900 212 2 35 247 2219829 1804 0 77 77 2948 900 212 4 37 249 2219829 1804 0 81 81 2948 900 214 - 4 28 242 2201206 1819 0 60 60 2957 909 214 - 2 30 244 2201206 1819 0 65 65 2957 909 214 0 32 246 2201206 1819 0 69 69 2957 909 214 2 34 248 2201206 1819 0 73 73 2957 909 214 4 36 250 2201206 1819 0 78 78 2957 909 216 - 4 27 243 2178859 1836 0 57 57 2965 917 216 - 2 29 245 2178859 1836 0 61 61 2965 917 216 0 31 247 2178859 1836 0 66 66 2965 917 216 2 33 249 2178859 1836 0 70 70 2965 917 216 4 35 251 2178859 1836 0 75 75 2965 917 218 - 4 26 244 2160236 1853 0 54 54 2974 926 218 - 2 28 246 2160236 1853 0 59 59 2974 926 218 0 30 248 2160236 1853 0 63 63 2974 926 218 2 32 250 2160236 1853 0 68 68 2974 926 218 4 34 252 2160236 1853 0 72 72 2974 926 220 - 4 25 245 2141613 1870 0 52 52 2982 934 220 - 2 27 247 2141613 1870 0 56 56 2982 934 220 0 29 249 2141613 1870 0 61 61 2982 934 220 2 31 251 2141613 1870 0 65 65 2982 934 220 4 33 253 2141613 1870 0 69 69 2982 934 full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 204 0 37 241 2309218 1734 0 84 84 2941 866 2004 mar 01 21 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 10 y scaler programming at ntsc, input frame size: 640 480, half anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 212 - 4 29 241 2219829 2704 2048 63 63 3399 327 212 - 2 31 243 2219829 2704 2048 67 67 3399 327 212 0 33 245 2219829 2704 2048 72 72 3399 327 212 2 35 247 2219829 2704 2048 77 77 3399 327 212 4 37 249 2219829 2704 2048 81 81 3399 327 214 - 4 28 242 2201206 2730 2048 60 60 3412 340 214 - 2 30 244 2201206 2730 2048 65 65 3412 340 214 0 32 246 2201206 2730 2048 69 69 3412 340 214 2 34 248 2201206 2730 2048 74 74 3412 340 214 4 36 250 2201206 2730 2048 78 78 3412 340 216 - 4 27 243 2178859 2756 2048 57 57 3424 352 216 - 2 29 245 2178859 2756 2048 62 62 3424 352 216 0 31 247 2178859 2756 2048 66 66 3424 352 216 2 33 249 2178859 2756 2048 71 71 3424 352 216 4 35 251 2178859 2756 2048 75 75 3424 352 218 - 4 26 244 2160236 2781 2048 55 55 3437 365 218 - 2 28 246 2160236 2781 2048 59 59 3437 365 218 0 30 248 2160236 2781 2048 63 63 3437 365 218 2 32 250 2160236 2781 2048 68 68 3437 365 218 4 34 252 2160236 2781 2048 72 72 3437 365 220 - 4 25 245 2141613 2807 2048 52 52 3450 378 220 - 2 27 247 2141613 2807 2048 57 57 3450 378 220 0 29 249 2141613 2807 2048 61 61 3450 378 220 2 31 251 2141613 2807 2048 65 65 3450 378 220 4 33 253 2141613 2807 2048 70 70 3450 378 full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 204 0 37 241 2309218 2602 2048 84 84 3348 276 2004 mar 01 22 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 11 y scaler programming at ntsc, input frame size: 640 480, no anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 212 - 4 29 241 2219829 3607 4095 63 64 3849 3362 212 - 2 31 243 2219829 3607 4095 68 69 3849 3362 212 0 33 245 2219829 3607 4095 72 73 3849 3362 212 2 35 247 2219829 3607 4095 77 78 3849 3362 212 4 37 249 2219829 3607 4095 81 82 3849 3362 214 - 4 28 242 2201206 3639 4095 60 61 3866 3413 214 - 2 30 244 2201206 3639 4095 65 66 3866 3413 214 0 32 246 2201206 3639 4095 69 70 3866 3413 214 2 34 248 2201206 3639 4095 74 75 3866 3413 214 4 36 250 2201206 3639 4095 78 79 3866 3413 216 - 4 27 243 2178859 3675 4095 57 58 3883 3464 216 - 2 29 245 2178859 3675 4095 62 63 3883 3464 216 0 31 247 2178859 3675 4095 66 67 3883 3464 216 2 33 249 2178859 3675 4095 71 72 3883 3464 216 4 35 251 2178859 3675 4095 75 76 3883 3464 218 - 4 26 244 2160236 3709 4095 55 56 3900 3515 218 - 2 28 246 2160236 3709 4095 59 60 3900 3515 218 0 30 248 2160236 3709 4095 64 65 3900 3515 218 2 32 250 2160236 3709 4095 68 69 3900 3515 218 4 34 252 2160236 3709 4095 73 74 3900 3515 220 - 4 25 245 2141613 3741 4095 52 53 3917 3566 220 - 2 27 247 2141613 3741 4095 57 58 3917 3566 220 0 29 249 2141613 3741 4095 61 62 3917 3566 220 2 31 251 2141613 3741 4095 65 66 3917 3566 220 4 33 253 2141613 3741 4095 70 71 3917 3566 full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 204 0 37 241 2309218 3471 4095 85 86 3781 3158 2004 mar 01 23 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 12 y scaler programming at ntsc, input frame size: 800 600, full anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 212 - 4 29 241 3551726 1443 0 79 79 2769 721 212 - 2 31 243 3551726 1443 0 84 84 2769 721 212 0 33 245 3551726 1443 0 90 90 2769 721 212 2 35 247 3551726 1443 0 96 96 2769 721 212 4 37 249 3551726 1443 0 102 102 2769 721 214 - 4 28 242 3518354 1457 0 75 75 2776 728 214 - 2 30 244 3518354 1457 0 81 81 2776 728 214 0 32 246 3518354 1457 0 86 86 2776 728 214 2 34 248 3518354 1457 0 92 92 2776 728 214 4 36 250 3518354 1457 0 98 98 2776 728 216 - 4 27 243 3484982 1470 0 72 72 2782 734 216 - 2 29 245 3484982 1470 0 77 77 2782 734 216 0 31 247 3484982 1470 0 82 82 2782 734 216 2 33 249 3484982 1470 0 88 88 2782 734 216 4 35 251 3484982 1470 0 94 94 2782 734 218 - 4 26 244 3451610 1484 0 68 68 2789 741 218 - 2 28 246 3451610 1484 0 73 73 2789 741 218 0 30 248 3451610 1484 0 79 79 2789 741 218 2 32 250 3451610 1484 0 85 85 2789 741 218 4 34 252 3451610 1484 0 90 90 2789 741 220 - 4 25 245 3423006 1497 0 65 65 2796 748 220 - 2 27 247 3423006 1497 0 71 71 2796 748 220 0 29 249 3423006 1497 0 76 76 2796 748 220 2 31 251 3423006 1497 0 81 81 2796 748 220 4 33 253 3423006 1497 0 87 87 2796 748 full size (horizontal size: 710 pixels) 241 0 18 259 3122659 1642 0 42 42 2867 819 small size (horizontal size: 620 pixels) 204 0 37 241 3689981 1389 0 106 106 2742 694 2004 mar 01 24 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 13 y scaler programming at ntsc, input frame size: 800 600, half anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 212 - 4 29 241 3551726 2165 2048 79 79 3129 57 212 - 2 31 243 3551726 2165 2048 85 85 3129 57 212 0 33 245 3551726 2165 2048 91 91 3129 57 212 2 35 247 3551726 2165 2048 96 96 3129 57 212 4 37 249 3551726 2165 2048 102 102 3129 57 214 - 4 28 242 3518354 2185 2048 75 75 3140 68 214 - 2 30 244 3518354 2185 2048 81 81 3140 68 214 0 32 246 3518354 2185 2048 87 87 3140 68 214 2 34 248 3518354 2185 2048 92 92 3140 68 214 4 36 250 3518354 2185 2048 98 98 3140 68 216 - 4 27 243 3484982 2205 2048 72 72 3150 78 216 - 2 29 245 3484982 2205 2048 77 77 3150 78 216 0 31 247 3484982 2205 2048 83 83 3150 78 216 2 33 249 3484982 2205 2048 89 89 3150 78 216 4 35 251 3484982 2205 2048 94 94 3150 78 218 - 4 26 244 3451610 2226 2048 68 68 3160 88 218 - 2 28 246 3451610 2226 2048 74 74 3160 88 218 0 30 248 3451610 2226 2048 80 80 3160 88 218 2 32 250 3451610 2226 2048 85 85 3160 88 218 4 34 252 3451610 2226 2048 90 90 3160 88 220 - 4 25 245 3423006 2246 2048 65 65 3170 98 220 - 2 27 247 3423006 2246 2048 71 71 3170 98 220 0 29 249 3423006 2246 2048 76 76 3170 98 220 2 31 251 3423006 2246 2048 81 81 3170 98 220 4 33 253 3423006 2246 2048 87 87 3170 98 full size (horizontal size: 710 pixels) 241 0 18 259 3122659 2461 2048 42 42 3277 205 small size (horizontal size: 620 pixels) 204 0 37 241 3689981 2083 2048 106 106 3089 17 2004 mar 01 25 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 14 y scaler programming at ntsc, input frame size: 800 600, no anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 212 - 4 29 241 3551726 2887 4095 79 80 3490 2282 212 - 2 31 243 3551726 2887 4095 85 86 3490 2282 212 0 33 245 3551726 2887 4095 91 92 3490 2282 212 2 35 247 3551726 2887 4095 96 97 3490 2282 212 4 37 249 3551726 2887 4095 102 103 3490 2282 214 - 4 28 242 3518354 2912 4095 76 77 3504 2323 214 - 2 30 244 3518354 2912 4095 81 82 3504 2323 214 0 32 246 3518354 2912 4095 87 88 3504 2323 214 2 34 248 3518354 2912 4095 92 93 3504 2323 214 4 36 250 3518354 2912 4095 98 99 3504 2323 216 - 4 27 243 3484982 2941 4095 72 73 3517 2364 216 - 2 29 245 3484982 2941 4095 78 79 3517 2364 216 0 31 247 3484982 2941 4095 83 84 3517 2364 216 2 33 249 3484982 2941 4095 89 90 3517 2364 216 4 35 251 3484982 2941 4095 94 95 3517 2364 218 - 4 26 244 3451610 2969 4095 69 70 3531 2405 218 - 2 28 246 3451610 2969 4095 74 75 3531 2405 218 0 30 248 3451610 2969 4095 80 81 3531 2405 218 2 32 250 3451610 2969 4095 85 86 3531 2405 218 4 34 252 3451610 2969 4095 90 91 3531 2405 220 - 4 25 245 3423006 2994 4095 65 66 3544 2446 220 - 2 27 247 3423006 2994 4095 71 72 3544 2446 220 0 29 249 3423006 2994 4095 76 77 3544 2446 220 2 31 251 3423006 2994 4095 82 83 3544 2446 220 4 33 253 3423006 2994 4095 87 88 3544 2446 full size (horizontal size: 710 pixels) 241 0 18 259 3122659 3282 4095 42 43 3687 2875 small size (horizontal size: 620 pixels) 204 0 37 241 3689981 2778 4095 106 107 3436 2119 2004 mar 01 26 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 15 y scaler programming at pal, input frame size: 640 400, full anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 255 - 4 35 290 1528590 2600 0 52 52 3347 1299 255 - 2 37 292 1528590 2602 0 55 55 3347 1299 255 0 39 294 1528590 2602 0 59 59 3347 1299 255 2 41 296 1528590 2602 0 62 62 3347 1299 255 4 43 298 1528590 2602 0 65 65 3347 1299 257 - 4 34 291 1516163 2621 0 50 50 3357 1309 257 - 2 36 293 1516163 2623 0 53 53 3357 1309 257 0 38 295 1516163 2623 0 57 57 3357 1309 257 2 40 297 1516163 2623 0 60 60 3357 1309 257 4 42 299 1516163 2623 0 63 63 3357 1309 259 - 4 33 292 1506842 2641 0 49 49 3367 1319 259 - 2 35 294 1506842 2641 0 52 52 3367 1319 259 0 37 296 1506842 2641 0 55 55 3367 1319 259 2 39 298 1506842 2641 0 58 58 3367 1319 259 4 41 300 1506842 2641 0 61 61 3367 1319 261 - 4 32 293 1494414 2661 0 47 47 3377 1329 261 - 2 34 295 1494414 2661 0 50 50 3377 1329 261 0 36 297 1494414 2661 0 53 53 3377 1329 261 2 38 299 1494414 2661 0 56 56 3377 1329 261 4 40 301 1494414 2661 0 59 59 3377 1329 263 - 4 31 294 1481987 2684 0 45 45 3387 1339 263 - 2 33 296 1481987 2684 0 48 48 3387 1339 263 0 35 298 1481987 2684 0 51 51 3387 1339 263 2 37 300 1481987 2684 0 54 54 3387 1339 263 4 39 302 1481987 2684 0 57 57 3387 1339 full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 250 0 41 291 1559659 2549 0 63 63 3321 1273 2004 mar 01 27 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 16 y scaler programming at pal, input frame size: 640 400, half anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 255 - 4 35 290 1528590 3346 1170 53 53 3996 924 255 - 2 37 292 1528590 3346 1170 56 56 3996 924 255 0 39 294 1528590 3346 1170 59 59 3996 924 255 2 41 296 1528590 3346 1170 62 62 3996 924 255 4 43 298 1528590 3346 1170 65 65 3996 924 257 - 4 34 291 1516163 3360 1150 51 51 4012 940 257 - 2 36 293 1516163 3360 1150 54 54 4012 940 257 0 38 295 1516163 3360 1150 57 57 4012 940 257 2 40 297 1516163 3360 1150 60 60 4012 940 257 4 42 299 1516163 3360 1150 63 63 4012 940 259 - 4 33 292 1506842 3362 1120 49 49 4070 998 259 - 2 35 294 1506842 3362 1120 52 52 4070 998 259 0 37 296 1506842 3362 1120 55 55 4070 998 259 2 39 298 1506842 3362 1120 58 58 4070 998 259 4 41 300 1506842 3362 1120 61 61 4070 998 261 - 4 32 293 1494414 3378 1100 47 47 4042 970 261 - 2 34 295 1494414 3378 1100 50 50 4042 970 261 0 36 297 1494414 3378 1100 53 53 4042 970 261 2 38 299 1494414 3378 1100 56 56 4042 970 261 4 40 301 1494414 3378 1100 59 59 4042 970 263 - 4 31 294 1481987 3384 1070 45 45 4057 985 263 - 2 33 296 1481987 3384 1070 48 48 4057 985 263 0 35 298 1481987 3384 1070 51 51 4057 985 263 2 37 300 1481987 3384 1070 54 54 4057 985 263 4 39 302 1481987 3384 1070 57 57 4057 985 full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 250 0 41 291 1559659 3322 1240 63 63 3707 1039 2004 mar 01 28 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 17 y scaler programming at pal, input frame size: 640 400, no anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 255 - 4 35 290 1528590 4095 2350 53 53 4092 869 255 - 2 37 292 1528590 4095 2350 56 56 4092 869 255 0 39 294 1528590 4095 2350 59 59 4092 869 255 2 41 296 1528590 4095 2350 62 62 4092 869 255 4 43 298 1528590 4095 2350 65 65 4092 869 257 - 4 34 291 1516163 4095 2300 51 51 4092 894 257 - 2 36 293 1516163 4095 2300 54 54 4092 894 257 0 38 295 1516163 4095 2300 57 57 4092 894 257 2 40 297 1516163 4095 2300 60 60 4092 894 257 4 42 299 1516163 4095 2300 63 63 4092 894 259 - 4 33 292 1506842 4093 2250 49 49 4092 919 259 - 2 35 294 1506842 4093 2250 52 52 4092 919 259 0 37 296 1506842 4093 2250 55 55 4092 919 259 2 39 298 1506842 4091 2250 58 58 4092 919 259 4 42 301 1506842 4091 2250 63 63 4092 919 261 - 4 32 293 1494414 4094 2200 47 47 4092 944 261 - 2 34 295 1494414 4094 2200 50 50 4092 944 261 0 36 297 1494414 4094 2200 53 53 4092 944 261 2 38 299 1494414 4093 2200 56 56 4092 944 261 4 40 301 1494414 4093 2200 59 59 4092 944 263 - 4 31 294 1481987 4092 2150 45 45 4091 968 263 - 2 33 296 1481987 4092 2150 48 48 4091 968 263 0 35 298 1481987 4092 2150 51 51 4091 968 263 2 37 300 1481987 4092 2150 54 54 4091 968 263 4 39 302 1481987 4092 2150 57 57 4091 968 full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 250 0 41 291 1559659 4087 2470 63 63 4089 806 2004 mar 01 29 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 18 y scaler programming at pal, input frame size: 640 480, full anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 255 - 4 35 290 1833066 2168 0 63 63 3131 1083 255 - 2 37 292 1833066 2168 0 67 67 3131 1083 255 0 39 294 1833066 2168 0 71 71 3131 1083 255 2 41 296 1833066 2168 0 74 74 3131 1083 255 4 43 298 1833066 2168 0 78 78 3131 1083 257 - 4 34 291 1820638 2185 0 61 61 3139 1091 257 - 2 36 293 1820638 2185 0 65 65 3139 1091 257 0 38 295 1820638 2185 0 69 69 3139 1091 257 2 40 297 1820638 2185 0 72 72 3139 1091 257 4 42 299 1820638 2185 0 76 76 3139 1091 259 - 4 33 292 1805104 2202 0 58 58 3148 1100 259 - 2 35 294 1805104 2202 0 62 62 3148 1100 259 0 37 296 1805104 2202 0 66 66 3148 1100 259 2 39 298 1805104 2204 0 70 70 3148 1100 259 4 41 300 1805104 2202 0 73 73 3148 1100 261 - 4 32 293 1792676 2219 0 56 56 3156 1108 261 - 2 34 295 1792676 2219 0 60 60 3156 1108 261 0 36 297 1792676 2219 0 64 64 3156 1108 261 2 38 299 1792676 2219 0 67 67 3156 1108 261 4 40 301 1792676 2219 0 71 71 3156 1108 263 - 4 31 294 1777142 2238 0 54 54 3165 1117 263 - 2 33 296 1777142 2238 0 58 58 3165 1117 263 0 35 298 1777142 2238 0 61 61 3165 1117 263 2 37 300 1777142 2238 0 65 65 3165 1117 263 4 39 302 1777142 2238 0 69 69 3165 1117 full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 250 0 41 291 1870348 2125 0 76 76 3110 1062 2004 mar 01 30 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 19 y scaler programming at pal, input frame size: 640 480, half anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 255 - 4 35 290 1833066 3254 2048 63 63 3673 601 255 - 2 37 292 1833066 3254 2048 67 67 3673 601 255 0 39 294 1833066 3254 2048 71 71 3673 601 255 2 41 296 1833066 3254 2048 75 75 3673 601 255 4 43 298 1833066 3254 2048 79 79 3673 601 257 - 4 34 291 1820638 3277 2048 61 61 3686 614 257 - 2 36 293 1820638 3277 2048 65 65 3686 614 257 0 38 295 1820638 3277 2048 69 69 3686 614 257 2 40 297 1820638 3277 2048 72 72 3686 614 257 4 42 299 1820638 3277 2048 76 76 3686 614 259 - 4 33 292 1805104 3305 2048 59 59 3698 626 259 - 2 35 294 1805104 3305 2048 63 63 3698 626 259 0 37 296 1805104 3305 2048 66 66 3698 626 259 2 39 298 1805104 3305 2048 70 70 3698 626 259 4 41 300 1805104 3305 2048 74 74 3698 626 261 - 4 32 293 1792676 3328 2048 57 57 3711 639 261 - 2 34 295 1792676 3328 2048 60 60 3711 639 261 0 36 297 1792676 3328 2048 64 64 3711 639 261 2 38 299 1792676 3328 2048 68 68 3711 639 261 4 40 301 1792676 3328 2048 71 71 3711 639 263 - 4 31 294 1777142 3354 2048 54 54 3724 652 263 - 2 33 296 1777142 3354 2048 58 58 3724 652 263 0 35 298 1777142 3354 2048 61 61 3724 652 263 2 37 300 1777142 3354 2048 65 65 3724 652 263 4 39 302 1777142 3354 2048 69 69 3724 652 full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 250 0 41 291 1870348 3108 1890 76 76 3600 607 2004 mar 01 31 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 20 y scaler programming at pal, input frame size: 640 480, no anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 255 - 4 35 290 1833066 4093 3630 64 64 4091 228 255 - 2 37 292 1833066 4093 3630 67 67 4091 228 255 0 39 294 1833066 4093 3630 71 71 4091 228 255 2 41 296 1833066 4093 3630 75 75 4091 228 255 4 43 298 1833066 4093 3630 79 79 4091 228 257 - 4 34 291 1820638 4090 3570 61 61 4091 258 257 - 2 36 293 1820638 4090 3570 65 65 4091 258 257 0 38 295 1820638 4090 3570 69 69 4091 258 257 2 40 297 1820638 4090 3570 73 73 4091 258 257 4 42 299 1820638 4090 3570 76 76 4091 258 259 - 4 33 292 1805104 4092 3510 59 59 4091 288 259 - 2 35 294 1805104 4092 3510 63 63 4091 288 259 0 37 296 1805104 4092 3510 66 66 4091 288 259 2 39 298 1805104 4092 3510 70 70 4091 288 259 4 41 300 1805104 4092 3510 74 74 4091 288 261 - 4 32 293 1792676 4088 3450 57 57 4091 318 261 - 2 34 295 1792676 4088 3450 60 60 4091 318 261 0 36 297 1792676 4088 3450 64 64 4091 318 261 2 38 299 1792676 4088 3450 68 68 4091 318 261 4 40 301 1792676 4088 3450 71 71 4091 318 263 - 4 31 294 1777142 4095 3400 54 54 4095 345 263 - 2 33 296 1777142 4095 3400 58 58 4095 345 263 0 35 298 1777142 4095 3400 62 62 4095 345 263 2 37 300 1777142 4095 3400 65 65 4095 345 263 4 39 302 1777142 4095 3400 69 69 4095 345 full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0 small size (horizontal size: 620 pixels) 250 0 41 291 1870348 4088 3780 76 76 4090 152 2004 mar 01 32 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 21 y scaler programming at pal, input frame size: 800 600, full anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 255 - 4 35 290 2930917 1736 0 79 79 2915 867 255 - 2 37 292 2930917 1736 0 84 84 2915 867 255 0 39 294 2930917 1736 0 89 89 2915 867 255 2 41 296 2930917 1736 0 93 93 2915 867 255 4 43 298 2930917 1736 0 98 98 2915 867 257 - 4 34 291 2911033 1749 0 77 77 2922 874 257 - 2 36 293 2911033 1749 0 81 81 2922 874 257 0 38 295 2911033 1749 0 86 86 2922 874 257 2 40 297 2911033 1749 0 91 91 2922 874 257 4 42 299 2911033 1749 0 95 95 2922 874 259 - 4 33 292 2887172 1763 0 73 73 2929 881 259 - 2 35 294 2887172 1763 0 78 78 2929 881 259 0 37 296 2887172 1763 0 83 83 2929 881 259 2 39 298 2887172 1763 0 87 87 2929 881 259 4 41 300 2887172 1763 0 92 92 2929 881 261 - 4 32 293 2863311 1778 0 71 71 2935 887 261 - 2 34 295 2863311 1778 0 75 75 2935 887 261 0 36 297 2863311 1778 0 80 80 2935 887 261 2 38 299 2863311 1778 0 85 85 2935 887 261 4 40 301 2863311 1778 0 89 89 2935 887 263 - 4 31 294 2843427 1790 0 68 68 2942 894 263 - 2 33 296 2843427 1790 0 72 72 2942 894 263 0 35 298 2843427 1790 0 77 77 2942 894 263 2 37 300 2843427 1790 0 82 82 2942 894 263 4 39 302 2843427 1790 0 86 86 2942 894 full size (horizontal size: 702 pixels) 288 0 22 310 2596864 1960 0 43 43 3027 979 small size (horizontal size: 620 pixels) 250 0 41 291 2990569 1701 0 95 95 2898 850 2004 mar 01 33 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 22 y scaler programming at pal, input frame size: 800 600, half anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 255 - 4 35 290 2930917 2604 2048 80 80 3349 277 255 - 2 37 292 2930917 2604 2048 84 84 3349 277 255 0 39 294 2930917 2604 2048 89 89 3349 277 255 2 41 296 2930917 2604 2048 94 94 3349 277 255 4 43 298 2930917 2604 2048 98 98 3349 277 257 - 4 34 291 2911033 2625 2048 77 77 3359 287 257 - 2 36 293 2911033 2625 2048 82 82 3359 287 257 0 38 295 2911033 2625 2048 86 86 3359 287 257 2 40 297 2911033 2625 2048 91 91 3359 287 257 4 42 299 2911033 2625 2048 96 96 3359 287 259 - 4 33 292 2887172 2645 2048 74 74 3369 297 259 - 2 35 294 2887172 2645 2048 79 79 3369 297 259 0 37 296 2887172 2645 2048 83 83 3369 297 259 2 39 298 2887172 2645 2048 88 88 3369 297 259 4 41 300 2887172 2645 2048 92 92 3369 297 261 - 4 32 293 2863311 2666 2048 71 71 3379 307 261 - 2 34 295 2863311 2666 2048 75 75 3379 307 261 0 36 297 2863311 2666 2048 80 80 3379 307 261 2 38 299 2863311 2666 2048 85 85 3379 307 261 4 40 301 2863311 2666 2048 89 89 3379 307 263 - 4 31 294 2843427 2686 2048 68 68 3390 318 263 - 2 33 296 2843427 2686 2048 73 73 3390 318 263 0 35 298 2843427 2686 2048 77 77 3390 318 263 2 37 300 2843427 2686 2048 82 82 3390 318 263 4 39 302 2843427 2686 2048 86 86 3390 318 full size (horizontal size: 702 pixels) 288 0 22 310 2596864 2940 2048 43 43 3517 445 small size (horizontal size: 620 pixels) 250 0 41 291 2990569 2553 2048 96 96 3323 251 2004 mar 01 34 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 23 y scaler programming at pal, input frame size: 800 600, no anti-?icker ?lter tv line offset fal lal pcl yinc yskip yofso yofse yiwgto yiwgte regular size (horizontal tv size: 640 pixels, offset 10 pixels) 255 - 4 35 290 2930917 3473 4095 80 81 3783 3161 255 - 2 37 292 2930917 3473 4095 84 85 3783 3161 255 0 39 294 2930917 3473 4095 89 90 3783 3161 255 2 41 296 2930917 3473 4095 94 95 3783 3161 255 4 43 298 2930917 3473 4095 99 100 3783 3161 257 - 4 34 291 2911033 3500 4095 77 78 3796 3202 257 - 2 36 293 2911033 3500 4095 82 83 3796 3202 257 0 38 295 2911033 3500 4095 87 88 3796 3202 257 2 40 297 2911033 3500 4095 91 92 3796 3202 257 4 42 299 2911033 3500 4095 96 97 3796 3202 259 - 4 33 292 2887172 3527 4095 74 75 3810 3242 259 - 2 35 294 2887172 3527 4095 79 80 3810 3242 259 0 37 296 2887172 3527 4095 83 84 3810 3242 259 2 39 298 2887172 3527 4095 88 89 3810 3242 259 4 41 300 2887172 3527 4095 93 94 3810 3242 261 - 4 32 293 2863311 3555 4095 71 72 3823 3284 261 - 2 34 295 2863311 3555 4095 76 77 3823 3284 261 0 36 297 2863311 3555 4095 80 81 3823 3284 261 2 38 299 2863311 3555 4095 85 86 3823 3284 261 4 40 301 2863311 3555 4095 89 90 3823 3284 263 - 4 31 294 2843427 3582 4095 68 69 3837 3324 263 - 2 33 296 2843427 3582 4095 73 74 3837 3324 263 0 35 298 2843427 3582 4095 78 79 3837 3324 263 2 37 300 2843427 3582 4095 82 83 3837 3324 263 4 39 302 2843427 3582 4095 87 88 3837 3324 full size (horizontal size: 702 pixels) 288 0 22 310 2596864 3923 4095 44 45 4007 3836 small size (horizontal size: 620 pixels) 250 0 41 291 2990569 3405 4095 96 97 3748 3059 2004 mar 01 35 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 24 itu-r bt.601 signal component levels note 1. transformation: a) r = y + 1.3707 (c r - 128) b) g=y - 0.3365 (c b - 128) - 0.6982 (c r - 128) c) b = y + 1.7324 (c b - 128). table 25 pin assignment for input format 0 table 26 pin assignment for input format 1 table 27 pin assignment for input format 2 table 28 pin assignment for input format 3 colour signals (1) yc b c r rgb white 235 128 128 235 235 235 yellow 210 16 146 235 235 16 cyan 170 166 16 16 235 235 green 145 54 34 16 235 16 magenta 106 202 222 235 16 235 red 81 90 240 235 16 16 blue 41 240 110 16 16 235 black 16 128 128 16 16 16 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced rgb/c b -y-c r pin falling clock edge rising clock edge pd11 g3/y3 r7/c r 7 pd10 g2/y2 r6/c r 6 pd9 g1/y1 r5/c r 5 pd8 g0/y0 r4/c r 4 pd7 b7/c b 7 r3/c r 3 pd6 b6/c b 6 r2/c r 2 pd5 b5/c b 5 r1/c r 1 pd4 b4/c b 4 r0/c r 0 pd3 b3/c b 3 g7/y7 pd2 b2/c b 2 g6/y6 pd1 b1/c b 1 g5/y5 pd0 b0/c b 0 g4/y4 5 + 5 + 5-bit 4 : 4 : 4 non-interlaced rgb pin falling clock edge rising clock edge pd7 g2 x pd6 g1 r4 pd5 g0 r3 pd4 b4 r2 pd3 b3 r1 pd2 b2 r0 pd1 b1 g4 pd0 b0 g3 5 + 6 + 5-bit 4 : 4 : 4 non-interlaced rgb pin falling clock edge rising clock edge pd7 g2 r4 pd6 g1 r3 pd5 g0 r2 pd4 b4 r1 pd3 b3 r0 pd2 b2 g5 pd1 b1 g4 pd0 b0 g3 8 + 8 + 8-bit 4:2:2 non-interlaced c b -y-c r pin falling clock edge n rising clock edge n falling clock edge n+1 rising clock edge n+1 pd7 c b 7(0) y7(0) c r 7(0) y7(1) pd6 c b 6(0) y6(0) c r 6(0) y6(1) pd5 c b 5(0) y5(0) c r 5(0) y5(1) pd4 c b 4(0) y4(0) c r 4(0) y4(1) pd3 c b 3(0) y3(0) c r 3(0) y3(1) pd2 c b 2(0) y2(0) c r 2(0) y2(1) pd1 c b 1(0) y1(0) c r 1(0) y1(1) pd0 c b 0(0) y0(0) c r 0(0) y0(1) 2004 mar 01 36 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 29 pin assignment for input format 4 table 30 pin assignment for input format 5; note 1 note 1. x = dont care. table 31 pin assignment for input format 6 8 + 8 + 8-bit 4 : 2 : 2 interlaced c b -y-c r (itu-r bt.656, 27 mhz clock) pin rising clock edge n rising clock edge n+1 rising clock edge n+2 rising clock edge n+3 pd7 c b 7(0) y7(0) c r 7(0) y7(1) pd6 c b 6(0) y6(0) c r 6(0) y6(1) pd5 c b 5(0) y5(0) c r 5(0) y5(1) pd4 c b 4(0) y4(0) c r 4(0) y4(1) pd3 c b 3(0) y3(0) c r 3(0) y3(1) pd2 c b 2(0) y2(0) c r 2(0) y2(1) pd1 c b 1(0) y1(0) c r 1(0) y1(1) pd0 c b 0(0) y0(0) c r 0(0) y0(1) 8-bit non-interlaced index colour pin falling clock edge rising clock edge pd11 x x pd10 x x pd9 x x pd8 x x pd7 index7 x pd6 index6 x pd5 index5 x pd4 index4 x pd3 index3 x pd2 index2 x pd1 index1 x pd0 index0 x 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced rgb/c b -y-c r pin falling clock edge rising clock edge pd11 g4/y4 r7/c r 7 pd10 g3/y3 r6/c r 6 pd9 g2/y2 r5/c r 5 pd8 b7/c b 7 r4/c r 4 pd7 b6/c b 6 r3/c r 3 pd6 b5/c b 5 g7/y7 pd5 b4/c b 4 g6/y6 pd4 b3/c b 3 g5/y5 pd3 g0/y0 r2/c r 2 pd2 b2/c b 2 r1/c r 1 pd1 b1/c b 1 r0/c r 0 pd0 b0/c b 0 g1/y1 2004 mar 01 37 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 7.19 bit allocation map table 32 slave receiver (slave address 88h) register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0 status byte (read only) 00 ver2 ver1 ver0 ccrdo ccrde (1) fseq o_e null 01 to 15 (1) (1) (1) (1) (1) (1) (1) (1) common dac adjust ?ne 16 (1) (1) (1) (1) dacf3 dacf2 dacf1 dacf0 r dac adjust coarse 17 (1) (1) (1) rdacc4 rdacc3 rdacc2 rdacc1 rdacc0 g dac adjust coarse 18 (1) (1) (1) gdacc4 gdacc3 gdacc2 gdacc1 gdacc0 b dac adjust coarse 19 (1) (1) (1) bdacc4 bdacc3 bdacc2 bdacc1 bdacc0 msm threshold 1a msmt7 msmt6 msmt5 msmt4 msmt3 msmt2 msmt1 msmt0 monitor sense mode 1b msm (1) (1) (1) (1) rcomp gcomp bcomp chip id (02b or 03b, read only) 1c cid7 cid6 cid5 cid4 cid3 cid2 cid1 cid0 wide screen signal 26 wss7 wss6 wss5 wss4 wss3 wss2 wss1 wss0 wide screen signal 27 wsson (1) wss13 wss12 wss11 wss10 wss9 wss8 real-time control, burst start 28 (1) (1) bs5 bs4 bs3 bs2 bs1 bs0 sync reset enable, burst end 29 sres (1) be5 be4 be3 be2 be1 be0 copy generation 0 2a cg07 cg06 cg05 cg04 cg03 cg02 cg01 cg00 copy generation 1 2b cg15 cg14 cg13 cg12 cg11 cg10 cg09 cg08 cg enable, copy generation 2 2c cgen (1) (1) (1) cg19 cg18 cg17 cg16 output port control 2d vbsen cvbsen1 cvbsen0 cen encoff clk2en (1) (1) null 2e to 37 (1) (1) (1) (1) (1) (1) (1) (1) gain luminance for rgb 38 (1) (1) (1) gy4 gy3 gy2 gy1 gy0 gain colour difference for rgb 39 (1) (1) (1) gcd4 gcd3 gcd2 gcd1 gcd0 input port control 1 3a cbenb (1) (1) symp demoff csync y2c uv2c vps enable, input control 2 54 vpsen (1) (1) (1) (1) (1) edge2 edge1 vps byte 5 55 vps57 vps56 vps55 vps54 vps53 vps52 vps51 vps50 vps byte 11 56 vps117 vps116 vps115 vps114 vps113 vps112 vps111 vps110 vps byte 12 57 vps127 vps126 vps125 vps124 vps123 vps122 vps121 vps120 vps byte 13 58 vps137 vps136 vps135 vps134 vps133 vps132 vps131 vps130 vps byte 14 59 vps147 vps146 vps145 vps144 vps143 vps142 vps141 vps140 chrominance phase 5a chps7 chps6 chps5 chps4 chps3 chps2 chps1 chps0 gain u 5b gainu7 gainu6 gainu5 gainu4 gainu3 gainu2 gainu1 gainu0 2004 mar 01 38 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... gain v 5c gainv7 gainv6 gainv5 gainv4 gainv3 gainv2 gainv1 gainv0 gain u msb, black level 5d gainu8 (1) blckl5 blckl4 blckl3 blckl2 blckl1 blckl0 gain v msb, blanking level 5e gainv8 (1) blnnl5 blnnl4 blnnl3 blnnl2 blnnl1 blnnl0 ccr, blanking level vbi 5f ccrs1 ccrs0 blnvb5 blnvb4 blnvb3 blnvb2 blnvb1 blnvb0 null 60 (1) (1) (1) (1) (1) (1) (1) (1) standard control 61 downd downa (1) ygs (1) scbw pal fise burst amplitude 62 (1) bsta6 bsta5 bsta4 bsta3 bsta2 bsta1 bsta0 subcarrier 0 63 fsc07 fsc06 fsc05 fsc04 fsc03 fsc02 fsc01 fsc00 subcarrier 1 64 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc09 fsc08 subcarrier 2 65 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 subcarrier 3 66 fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 line 21 odd 0 67 l21o07 l21o06 l21o05 l21o04 l21o03 l21o02 l21o01 l21o00 line 21 odd 1 68 l21o17 l21o16 l21o15 l21o14 l21o13 l21o12 l21o11 l21o10 line 21 even 0 69 l21e07 l21e06 l21e05 l21e04 l21e03 l21e02 l21e01 l21e00 line 21 even 1 6a l21e17 l21e16 l21e15 l21e14 l21e13 l21e12 l21e11 l21e10 null 6b (1) (1) (1) (1) (1) (1) (1) (1) trigger control 6c htrig7 htrig6 htrig5 htrig4 htrig3 htrig2 htrig1 htrig0 trigger control 6d htrig10 htrig9 htrig8 vtrig4 vtrig3 vtrig2 vtrig1 vtrig0 multi control 6e (1) blckon phres1 phres0 ldel1 ldel0 flc1 flc0 closed caption, teletext enable 6f ccen1 ccen0 ttxen sccln4 sccln3 sccln2 sccln1 sccln0 active display window horizontal start 70 adwhs7 adwhs6 adwhs5 adwhs4 adwhs3 adwhs2 adwhs1 adwhs0 active display window horizontal end 71 adwhe7 adwhe6 adwhe5 adwhe4 adwhe3 adwhe2 adwhe1 adwhe0 msbs adwh 72 (1) adwhe10 adwhe9 adwhe8 (1) adwhs10 adwhs9 adwhs8 ttx request horizontal start 73 ttxhs7 ttxhs6 ttxhs5 ttxhs4 ttxhs3 ttxhs2 ttxhs1 ttxhs0 ttx request horizontal delay 74 (1) (1) (1) (1) ttxhd3 ttxhd2 ttxhd1 ttxhd0 csync advance 75 csynca4 csynca3 csynca2 csynca1 csynca0 (1) (1) (1) ttx odd request vertical start 76 ttxovs7 ttxovs6 ttxovs5 ttxovs4 ttxovs3 ttxovs2 ttxovs1 ttxovs0 ttx odd request vertical end 77 ttxove7 ttxove6 ttxove5 ttxove4 ttxove3 ttxove2 ttxove1 ttxove0 ttx even request vertical start 78 ttxevs7 ttxevs6 ttxevs5 ttxevs4 ttxevs3 ttxevs2 ttxevs1 ttxevs0 ttx even request vertical end 79 ttxeve7 ttxeve6 ttxeve5 ttxeve4 ttxeve3 ttxeve2 ttxeve1 ttxeve0 register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0 2004 mar 01 39 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... first active line 7a fal7 fal6 fal5 fal4 fal3 fal2 fal1 fal0 last active line 7b lal7 lal6 lal5 lal4 lal3 lal2 lal1 lal0 ttx mode, msb vertical 7c ttx60 lal8 (1) fal8 ttxeve8 ttxove8 ttxevs8 ttxovs8 null 7d (1) (1) (1) (1) (1) (1) (1) (1) disable ttx line 7e line12 line11 line10 line9 line8 line7 line6 line5 disable ttx line 7f line20 line19 line18 line17 line16 line15 line14 line13 fifo status (read only) 80 (1) (1) (1) (1) (1) (1) ovfl udfl pixel clock 0 81 pcl07 pcl06 pcl05 pcl04 pcl03 pcl02 pcl01 pcl00 pixel clock 1 82 pcl15 pcl14 pcl13 pcl12 pcl11 pcl10 pcl09 pcl08 pixel clock 2 83 pcl23 pcl22 pcl21 pcl20 pcl19 pcl18 pcl17 pcl16 null 84 to 8f (1) (1) (1) (1) (1) (1) (1) (1) horizontal offset 90 xofs7 xofs6 xofs5 xofs4 xofs3 xofs2 xofs1 xofs0 pixel number 91 xpix7 xpix6 xpix5 xpix4 xpix3 xpix2 xpix1 xpix0 vertical offset odd 92 yofso7 yofso6 yofso5 yofso4 yofso3 yofso2 yofso1 yofso0 vertical offset even 93 yofse7 yofse6 yofse5 yofse4 yofse3 yofse2 yofse1 yofse0 msbs 94 yofse9 yofse8 yofso9 yofso8 xpix9 xpix8 xofs9 xofs8 line number 95 ypix7 ypix6 ypix5 ypix4 ypix3 ypix2 ypix1 ypix0 scaler ctrl, mcb ypix 96 efs pcbn slave ilc yfil hsl ypix9 ypix8 sync control 97 hfs vfs ofs pfs ovs pvs ohs phs line length 98 hlen7 hlen6 hlen5 hlen4 hlen3 hlen2 hlen1 hlen0 input delay, msb line length 99 idel3 idel2 idel1 idel0 (1) hlen10 hlen9 hlen8 horizontal increment 9a xinc7 xinc6 xinc5 xinc4 xinc3 xinc2 xinc1 xinc0 vertical increment 9b yinc7 yinc6 yinc5 yinc4 yinc3 yinc2 yinc1 yinc0 msbs vertical and horizontal increment 9c yinc11 yinc10 yinc9 yinc8 xinc11 xinc10 xinc9 xinc8 weighting factor odd 9d yiwgto7 yiwgto6 yiwgto5 yiwgto4 yiwgto3 yiwgto2 yiwgto1 yiwgto0 weighting factor even 9e yiwgte7 yiwgte6 yiwgte5 yiwgte4 yiwgte3 yiwgte2 yiwgte1 yiwgte0 weighting factor msb 9f yiwgte11 yiwgte10 yiwgte9 yiwgte8 yiwgto11 yiwgto10 yiwgto9 yiwgto8 vertical line skip a0 yskip7 yskip6 yskip5 yskip4 yskip3 yskip2 yskip1 yskip0 blank enable for ni-bypass, vertical line skip msb a1 blen (1) (1) (1) yskip11 yskip10 yskip9 yskip8 border colour y a2 bcy7 bcy6 bcy5 bcy4 bcy3 bcy2 bcy1 bcy0 register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0 2004 mar 01 40 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. all unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. border colour u a3 bcu7 bcu6 bcu5 bcu4 bcu3 bcu2 bcu1 bcu0 border colour v a4 bcv7 bcv6 bcv5 bcv4 bcv3 bcv2 bcv1 bcv0 cursor colour 1 r f0 cc1r7 cc1r6 cc1r5 cc1r4 cc1r3 cc1r2 cc1r1 cc1r0 cursor colour 1 g f1 cc1g7 cc1g6 cc1g5 cc1g4 cc1g3 cc1g2 cc1g1 cc1g0 cursor colour 1 b f2 cc1b7 cc1b6 cc1b5 cc1b4 cc1b3 cc1b2 cc1b1 cc1b0 cursor colour 2 r f3 cc2r7 cc2r6 cc2r5 cc2r4 cc2r3 cc2r2 cc2r1 cc2r0 cursor colour 2 g f4 cc2g7 cc2g6 cc2g5 cc2g4 cc2g3 cc2g2 cc2g1 cc2g0 cursor colour 2 b f5 cc2b7 cc2b6 cc2b5 cc2b4 cc2b3 cc2b2 cc2b1 cc2b0 auxiliary cursor colour r f6 auxr7 auxr6 auxr5 auxr4 auxr3 auxr2 auxr1 auxr0 auxiliary cursor colour g f7 auxg7 auxg6 auxg5 auxg4 auxg3 auxg2 auxg1 auxg0 auxiliary cursor colour b f8 auxb7 auxb6 auxb5 auxb4 auxb3 auxb2 auxb1 auxb0 horizontal cursor position f9 xcp7 xcp6 xcp5 xcp4 xcp3 xcp2 xcp1 xcp0 horizontal hot spot, msb xcp fa xhs4 xhs3 xhs2 xhs1 xhs0 xcp10 xcp9 xcp8 vertical cursor position fb ycp7 ycp6 ycp5 ycp4 ycp3 ycp2 ycp1 ycp0 vertical hot spot, msb ycp fc yhs4 yhs3 yhs2 yhs1 yhs0 (1) ycp9 ycp8 input path control fd lutoff cmode lutl if2 if1 if0 matoff dfoff cursor bit map fe ram address (see table 106) colour look-up table ff ram address (see table 107) register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0 2004 mar 01 41 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 7.20 i 2 c-bus format table 33 i 2 c-bus write access to control registers; see table 38 table 34 i 2 c-bus write access to cursor bit map (subaddress feh); see table 38 table 35 i 2 c-bus write access to colour look-up table (subaddress ffh); see table 38 table 36 i 2 c-bus read access to control registers; see table 38 table 37 i 2 c-bus read access to cursor bit map or colour lut; see table 38 table 38 explanations of tables 33 to 37 notes 1. x is the read/write control bit; x = logic 0 is order to write; x = logic 1 is order to read. 2. if more than 1 byte of data is transmitted, then auto-increment of the subaddress is performed. 7.21 slave receiver table 39 subaddress 16h s 10001000 a subaddress a data 0 a -------- data n a p s 10001000 a feh a ram address a data 0 a -------- data n a p s 10001000 a ffh a ram address a data 0r a data 0g a data 0b a -------- p s 10001000 a subaddress a sr 1 0 0 01001 a data0 am -------- data n am p s 10001000 a feh or ffh a ram address a sr 10001001 a data0 am -------- data n am p code description s start condition sr repeated start condition 1000100x; note 1 slave address a acknowledge generated by the slave am acknowledge generated by the master subaddress; note 2 subaddress byte data data byte -------- continued data bytes and acknowledges p stop condition ram address start address for ram access data byte description dacf output level adjustment ?ne in 1% steps for all dacs; default after reset is 00h; see table 40 2004 mar 01 42 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 40 fine adjustment of dac output voltage table 41 subaddresses 17h to 19h table 42 subaddress 1ah binary gain (%) 0111 7 0110 6 0101 5 0100 4 0011 3 0010 2 0001 1 0000 0 1000 0 1001 - 1 1010 - 2 1011 - 3 1100 - 4 1101 - 5 1110 - 6 1111 - 7 data byte description rdacc output level coarse adjustment for red dac; default after reset is 1bh for output of c signal 00000b o 0.585 v to 11111b o 1.240 v at 37.5 w nominal for full-scale conversion gdacc output level coarse adjustment for green dac; default after reset is 1bh for output of vbs signal 00000b o 0.585 v to 11111b o 1.240 v at 37.5 w nominal for full-scale conversion bdacc output level coarse adjustment for blue dac; default after reset is 1fh for output of cvbs signal 00000b o 0.585 v to 11111b o 1.240 v at 37.5 w nominal for full-scale conversion data byte description msmt monitor sense mode threshold for dac output voltage, should be set to 70 2004 mar 01 43 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 43 subaddress 1bh table 44 subaddresses 26h and 27h table 45 subaddress 28h table 46 subaddress 29h data byte logic level description msm 0 monitor sense mode off; rcomp, gcomp and bcomp bits are not valid; default after reset 1 monitor sense mode on rcomp (read only) 0 check comparator at dac on pin red_cr_c is active, output is loaded 1 check comparator at dac on pin red_cr_c is inactive, output is not loaded gcomp (read only) 0 check comparator at dac on pin green_vbs_cvbs is active, output is loaded 1 check comparator at dac on pin green_vbs_cvbs is inactive, output is not loaded bcomp (read only) 0 check comparator at dac on pin blue_cb_cvbs is active, output is loaded 1 check comparator at dac on pin blue_cb_cvbs is inactive, output is not loaded data byte logic level description wss - wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved wsson 0 wide screen signalling output is disabled; default after reset 1 wide screen signalling output is enabled data byte logic level description remarks bs - starting point of burst in clock cycles pal: bs = 33 (21h); default after reset if strapping pin 13 tied to high ntsc: bs = 25 (19h); default after reset if strapping pin 13 tied to low data byte logic level description remarks sres 0 pin ttx_sres accepts a teletext bit stream (ttx) default after reset 1 pin ttx_sres accepts a sync reset input (sres) a high impulse resets synchronization of the encoder (?rst ?eld, ?rst line) be - ending point of burst in clock cycles pal: be = 29 (1dh); default after reset if strapping pin fsvgc tied to high ntsc: be = 29 (1dh); default after reset if strapping pin fsvgc tied to low 2004 mar 01 44 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 47 subaddresses 2ah to 2ch table 48 subaddress 2dh table 49 subaddresses 38h and 39h data byte logic level description cg - lsbs of the respective bytes are encoded immediately after run-in, the msbs of the respective bytes have to carry the crcc bits, in accordance with the de?nition of copy generation management system encoding format. cgen 0 copy generation data output is disabled; default after reset 1 copy generation data output is enabled data byte logic level description vbsen 0 pin green_vbs_cvbs provides a component green signal (cvbsen1 = 0) or cvbs signal (cvbsen1 = 1) 1 pin green_vbs_cvbs provides a luminance (vbs) signal; default after reset cvbsen1 0 pin green_vbs_cvbs provides a component green (g) or luminance (vbs) signal; default after reset 1 pin green_vbs_cvbs provides a cvbs signal cvbsen0 0 pin blue_cb_cvbs provides a component blue (b) or colour difference blue (c b ) signal 1 pin blue_cb_cvbs provides a cvbs signal; default after reset cen 0 pin red_cr_c provides a component red (r) or colour difference red (c r ) signal 1 pin red_cr_c provides a chrominance signal (c) as modulated subcarrier for s-video; default after reset encoff 0 encoder is active; default after reset 1 encoder bypass, dacs are provided with rgb signal after cursor insertion block clk2en 0 pin ttxrq_xclko2 provides a teletext request signal (ttxrq) 1 pin ttxrq_xclko2 provides the buffered crystal clock divided by two (13.5 mhz); default after reset data byte description gy4 to gy0 gain luminance of rgb (c r , y and c b ) output, ranging from (1 - 16 32 )to(1+ 15 32 ). suggested nominal value = 0, depending on external application. gcd4 to gcd0 gain colour difference of rgb (c r , y and c b ) output, ranging from (1 - 16 32 )to(1+ 15 32 ). suggested nominal value = 0, depending on external application. 2004 mar 01 45 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 50 subaddress 3ah table 51 subaddress 54h table 52 subaddresses 55h to 59h data byte logic level description cbenb 0 data from input ports is encoded 1 colour bar with ?xed colours is encoded symp 0 horizontal and vertical trigger is taken from fsvgc or both vsvgc and hsvgc; default after reset 1 horizontal and vertical trigger is decoded out of itu-r bt.656 compatible data at pd port demoff 0 y-c b -c r to rgb dematrix is active; default after reset 1y-c b -c r to rgb dematrix is bypassed csync 0 pin 26 provides a horizontal sync for non-interlaced vga components output (at pixclk) 1 pin 26 provides a composite sync for interlaced components output (at xtal clock) y2c 0 input luminance data is twos complement from pd input port 1 input luminance data is straight binary from pd input port; default after reset uv2c 0 input colour difference data is twos complement from pd input port 1 input colour difference data is straight binary from pd input port; default after reset data byte logic level description vpsen 0 video programming system data insertion is disabled; default after reset 1 video programming system data insertion in line 16 is enabled edge2 0 internal ppd2 data is sampled on the rising clock edge 1 internal ppd2 data is sampled on the falling clock edge; see tables 25 to 30; default after reset edge1 0 internal ppd1 data is sampled on the rising clock edge; see tables 25 to 30; default after reset 1 internal ppd1 data is sampled on the falling clock edge data byte description remarks vps5 ?fth byte of video programming system data in line 16; lsb ?rst; all other bytes are not relevant for vps vps11 eleventh byte of video programming system data vps12 twelfth byte of video programming system data vps13 thirteenth byte of video programming system data vps14 fourteenth byte of video programming system data 2004 mar 01 46 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 53 subaddress 5ah; note 1 note 1. the default after reset is 00h. table 54 subaddresses 5bh and 5dh table 55 subaddresses 5ch and 5eh table 56 subaddress 5dh notes 1. output black level/ire = blckl 2/6.29 + 28.9. 2. output black level/ire = blckl 2/6.18 + 26.5. data byte description value result chps phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees 6bh pal b/g and data from input ports in master mode 16h pal b/g and data from look-up table 25h ntsc m and data from input ports in master mode 46h ntsc m and data from look-up table data byte description conditions remarks gainu variable gain for c b signal; input representation in accordance with itu-r bt.601 white-to-black = 92.5 ire gainu = - 2.17 nominal to +2.16 nominal gainu = 0 output subcarrier of u contribution = 0 gainu = 118 (76h) output subcarrier of u contribution = nominal white-to-black = 100 ire gainu = - 2.05 nominal to +2.04 nominal gainu = 0 output subcarrier of u contribution = 0 gainu = 125 (7dh) output subcarrier of u contribution = nominal data byte description conditions remarks gainv variable gain for c r signal; input representation in accordance with itu-r bt.601 white-to-black = 92.5 ire gainv = - 1.55 nominal to +1.55 nominal gainv = 0 output subcarrier of v contribution = 0 gainv = 165 (a5h) output subcarrier of v contribution = nominal white-to-black = 100 ire gainv = - 1.46 nominal to +1.46 nominal gainv = 0 output subcarrier of v contribution = 0 gainv = 175 (afh) output subcarrier of v contribution = nominal data byte description conditions remarks blckl variable black level; input representation in accordance with itu-r bt.601 white-to-sync = 140 ire; note 1 recommended value: blckl = 58 (3ah) blckl = 0; note 1 output black level = 29 ire blckl = 63 (3fh); note 1 output black level = 49 ire white-to-sync = 143 ire; note 2 recommended value: blckl = 51 (33h) blckl = 0; note 2 output black level = 27 ire blckl = 63 (3fh); note 2 output black level = 47 ire 2004 mar 01 47 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 57 subaddress 5eh notes 1. output black level/ire = blnnl 2/6.29 + 25.4. 2. output black level/ire = blnnl 2/6.18 + 25.9; default after reset: 35h. table 58 subaddress 5fh table 59 logic levels and function of ccrs table 60 subaddress 61h data byte description conditions remarks blnnl variable blanking level white-to-sync = 140 ire; note 1 recommended value: blnnl = 46 (2eh) blnnl = 0; note 1 output blanking level = 25 ire blnnl = 63 (3fh); note 1 output blanking level = 45 ire white-to-sync = 143 ire; note 2 recommended value: blnnl = 53 (35h) blnnl = 0; note 2 output blanking level = 26 ire blnnl = 63 (3fh); note 2 output blanking level = 46 ire data byte description ccrs select cross-colour reduction ?lter in luminance; see table 59 blnvb variable blanking level during vertical blanking interval is typically identical to value of blnnl ccrs1 ccrs0 description 0 0 no cross-colour reduction; for overall transfer characteristic of luminance see fig.6 0 1 cross-colour reduction #1 active; for overall transfer characteristic see fig.6 1 0 cross-colour reduction #2 active; for overall transfer characteristic see fig.6 1 1 cross-colour reduction #3 active; for overall transfer characteristic see fig.6 data byte logic level description downd 0 digital core in normal operational mode; default after reset 1 digital core in sleep mode and is reactivated with an i 2 c-bus address downa 0 dacs in normal operational mode; default after reset 1 dacs in power-down mode ygs 0 luminance gain for white - black 100 ire 1 luminance gain for white - black 92.5 ire including 7.5 ire set-up of black scbw 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 4 and 5) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 4 and 5); default after reset pal 0 ntsc encoding (non-alternating v component) 1 pal encoding (alternating v component) fise 0 864 total pixel clocks per line 1 858 total pixel clocks per line 2004 mar 01 48 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 61 subaddress 62h table 62 subaddresses 63h to 66h (four bytes to program subcarrier frequency) note 1. examples: a) ntsc m: f fsc = 227.5, f llc = 1716 ? fsc = 569408543 (21f07c1fh). b) pal b/g: f fsc = 283.7516, f llc = 1728 ? fsc = 705268427 (2a098acbh). table 63 subaddresses 67h to 6ah table 64 subaddresses 6ch and 6dh data byte description conditions remarks bsta amplitude of colour burst; input representation in accordance with itu-r bt.601 white-to-black = 92.5 ire; burst = 40 ire; ntsc encoding recommended value: bsta = 63 (3fh) bsta = 0 to 2.02 nominal white-to-black = 92.5 ire; burst = 40 ire; pal encoding recommended value: bsta = 45 (2dh) bsta = 0 to 2.82 nominal white-to-black = 100 ire; burst = 43 ire; ntsc encoding recommended value: bsta = 67 (43h) bsta = 0 to 1.90 nominal white-to-black = 100 ire; burst = 43 ire; pal encoding recommended value: bsta = 47 (2fh); default after reset bsta = 0 to 3.02 nominal data byte description conditions remarks fsc0 to fsc3 f fsc = subcarrier frequency (in multiples of line frequency); f llc = clock frequency (in multiples of line frequency) ; note 1 fsc3 = most signi?cant byte; fsc0 = least signi?cant byte data byte description remarks l21o0 ?rst byte of captioning data, odd ?eld lsbs of the respective bytes are encoded immediately after run-in and framing code, the msbs of the respective bytes have to carry the parity bit, in accordance with the de?nition of line 21 encoding format. l21o1 second byte of captioning data, odd ?eld l21e0 ?rst byte of extended data, even ?eld l21e1 second byte of extended data, even ?eld data byte description htrig sets the horizontal trigger phase related to chip-internal horizontal input values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed; increasing htrig decreases delays of all internally generated timing signals; the default value is 0 fsc round f fsc f llc ------- - 2 32 ? ?? = 2004 mar 01 49 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 65 subaddress 6dh table 66 subaddress 6eh table 67 logic levels and function of phres table 68 logic levels and function of ldel table 69 logic levels and function of flc data byte description vtrig sets the vertical trigger phase related to chip-internal vertical input increasing vtrig decreases delays of all internally generated timing signals, measured in half lines; variation range of vtrig = 0 to 31 (1fh); the default value is 0 data byte logic level description blckon 0 encoder in normal operation mode; default after reset 1 output signal is forced to blanking level phres - selects the phase reset mode of the colour subcarrier generator; see table 67 ldel - selects the delay on luminance path with reference to chrominance path; see table 68 flc - ?eld length control; see table 69 data byte description phres1 phres0 0 0 no subcarrier reset 0 1 subcarrier reset every two lines 1 0 subcarrier reset every eight ?elds 1 1 subcarrier reset every four ?elds data byte description ldel1 ldel0 0 0 no luminance delay; default after reset 0 1 1 llc luminance delay 1 0 2 llc luminance delay 1 1 3 llc luminance delay data byte description flc1 flc0 0 0 interlaced 312.5 lines/?eld at 50 hz, 262.5 lines/?eld at 60 hz; default after reset 0 1 non-interlaced 312 lines/?eld at 50 hz, 262 lines/?eld at 60 hz 1 0 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz 1 1 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz 2004 mar 01 50 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 70 subaddress 6fh table 71 logic levels and function of ccen table 72 subaddresses 70h to 72h table 73 subaddress 73h table 74 subaddress 74h table 75 subaddress 75h data byte logic level description ccen - enables individual line 21 encoding; see table 71 ttxen 0 disables teletext insertion; default after reset 1 enables teletext insertion sccln - selects the actual line, where closed caption or extended data are encoded; line = (sccln + 4) for m-systems; line = (sccln + 1) for other systems data byte description ccen1 ccen0 0 0 line 21 encoding off; default after reset 0 1 enables encoding in ?eld 1 (odd) 1 0 enables encoding in ?eld 2 (even) 1 1 enables encoding in both ?elds data byte description adwhs active display window horizontal start; de?nes the start of the active tv display portion after the border colour values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed adwhe active display window horizontal end; de?nes the end of the active tv display portion before the border colour values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed data byte description remarks ttxhs start of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0); see fig.14 ttxhs = 42h; is default after reset if strapped to pal ttxhs = 54h; is default after reset if strapped to ntsc data byte description remarks ttxhd indicates the delay in clock cycles between rising edge of ttxrq output signal on pin ttxrq_xclko2 (clk2en = 0) and valid data at pin ttx_sres minimum value: ttxhd = 2; is default after reset data byte description csynca advanced composite sync against rgb output from 0 xtal clocks to 31 xtal clocks 2004 mar 01 51 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 76 subaddresses 76h, 77h and 7ch table 77 subaddresses 78h, 79h and 7ch table 78 subaddresses 7ah to 7ch table 79 subaddress 7ch table 80 subaddresses 7eh and 7fh data byte description remarks ttxovs ?rst line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in odd ?eld ttxovs = 05h; is default after reset if strapped to pal ttxovs = 06h; is default after reset if strapped to ntsc line = (ttxovs + 4) for m-systems line = (ttxovs + 1) for other systems ttxove last line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in odd ?eld ttxove = 16h; is default after reset if strapped to pal ttxove = 10h; is default after reset if strapped to ntsc line = (ttxove + 3) for m-systems line = ttxove for other systems data byte description remarks ttxevs ?rst line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in even ?eld ttxevs = 04h; is default after reset if strapped to pal ttxevs = 05h; is default after reset if strapped to ntsc line = (ttxevs + 4) for m-systems line = (ttxevs + 1) for other systems ttxeve last line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in even ?eld ttxeve = 16h; is default after reset if strapped to pal ttxeve = 10h; is default after reset if strapped to ntsc line = (ttxeve + 3) for m-systems line = ttxeve for other systems data byte description fal ?rst active line = fal + 4 for m-systems and fal + 1 for other systems, measured in lines fal = 0 coincides with the ?rst ?eld synchronization pulse lal last active line = lal + 3 for m-systems and lal for other system, measured in lines lal = 0 coincides with the ?rst ?eld synchronization pulse data byte logic level description ttx60 0 enables nabts (fise = 1) or european ttx (fise = 0); default after reset 1 enables world standard teletext 60 hz (fise = 1) data byte description line individual lines in both ?elds (pal counting) can be disabled for insertion of teletext by the respective bits, disabled line = linexx (50 hz ?eld rate) this bit mask is effective only if the lines are enabled by ttxovs/ttxove and ttxevs/ttxeve 2004 mar 01 52 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 81 subaddresses 81h to 83h table 82 subaddresses 90h and 94h table 83 subaddresses 91h and 94h table 84 subaddresses 92h and 94h table 85 subaddresses 93h and 94h table 86 subaddresses 95h and 96h data byte description pcl de?nes the frequency of the synthesized pixel clock pixclko; ; f xtal = 27 mhz nominal, e.g. 640 480 to ntsc m: pcl = 20f63bh; 640 480 to pal b/g: pcl = 1b5a73h (as by strapping pins) data byte description xofs horizontal offset; de?nes the number of pixclks from horizontal sync (hsvgc) output to composite blanking ( cbo) output data byte description xpix pixel in x direction; de?nes half the number of active pixels per input line (identical to the length of cbo pulses) data byte description yofso vertical offset in odd ?eld; de?nes (in the odd ?eld) the number of lines from vsvgc to ?rst line with active cbo; if no lut data is requested, the ?rst active cbo will be output at yofso + 2; usually, yofso = yofse with the exception of extreme vertical downscaling and interlacing data byte description yofse vertical offset in even ?eld; de?nes (in the even ?eld) the number of lines from vsvgc to ?rst line with active cbo; if no lut data is requested, the ?rst active cbo will be output at yofse + 2; usually, yofse = yofso with the exception of extreme vertical downscaling and interlacing data byte description ypix de?nes the number of requested input lines from the feeding device; number of requested lines = ypix + yofse - yofso f pixclk pcl 2 24 ----------- f xtal ? ?? 8 = 2004 mar 01 53 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 87 subaddress 96h table 88 subaddress 97h data byte logic level description efs 0 frame sync signal at pin fsvgc ignored in slave mode 1 frame sync signal at pin fsvgc accepted in slave mode pcbn 0 normal polarity of cbo signal (high during active video) 1 inverted polarity of cbo signal (low during active video) slave 0 the saa7102; saa7103 is timing master to the graphics controller 1 the saa7102; saa7103 is timing slave to the graphics controller ilc 0 if hardware cursor insertion is active, set low for non-interlaced input signals 1 if hardware cursor insertion is active, set high for interlaced input signals yfil 0 luminance sharpness booster disabled 1 luminance sharpness booster enabled hsl 0 normal trigger event handling of the horizontal state machine, if the saa7102; saa7103 is slave to hsvgc input 1 trigger event for horizontal state machine is shifted 128 pixclks in advance, adapted to a late hsvgc in slave mode data byte logic level description hfs 0 horizontal sync is directly derived from input signal (slave mode) at pin hsvgc 1 horizontal sync is derived from a frame sync signal (slave mode) at pin fsvgc (only if efs is set high) vfs 0 vertical sync (?eld sync) is directly derived from input signal (slave mode) at pin vsvgc 1 vertical sync (?eld sync) is derived from a frame sync signal (slave mode) at pin fsvgc (only if efs is set high) ofs 0 pin fsvgc is switched to input 1 pin fsvgc is switched to active output pfs 0 polarity of signal at pin fsvgc in output mode (master mode) is active high; rising edge of the input signal is used in slave mode 1 polarity of signal at pin fsvgc in output mode (master mode) is active low; falling edge of the input signal is used in slave mode ovs 0 pin vsvgc is switched to input 1 pin vsvgc is switched to active output pvs 0 polarity of signal at pin vsvgc in output mode (master mode) is active high; rising edge of the input signal is used in slave mode 1 polarity of signal at pin vsvgc in output mode (master mode) is active low; falling edge of the input signal is used in slave mode 2004 mar 01 54 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 89 subaddresses 98h and 99h table 90 subaddress 99h table 91 subaddresses 9ah and 9ch table 92 subaddresses 9bh and 9ch table 93 subaddresses 9dh and 9fh table 94 subaddresses 9eh and 9fh ohs 0 pin hsvgc is switched to input 1 pin hsvgc is switched to active output phs 0 polarity of signal at pin hsvgc in output mode (master mode) is active high; rising edge of the input signal is used in slave mode 1 polarity of signal at pin hsvgc in output mode (master mode) is active low; falling edge of the input signal is used in slave mode data byte description hlen horizontal length; data byte description idel input delay; de?nes the distance in pixclks between the active edge of cbo and the ?rst received valid pixel data byte description xinc incremental fraction of the horizontal scaling engine; data byte description yinc incremental fraction of the vertical scaling engine; data byte description yiwgto weighting factor for the ?rst line of the odd ?eld; data byte description yiwgte weighting factor for the ?rst line of the even ?eld; data byte logic level description hlen number of pixclks line ---------------------------------------------------- - 1 C = xinc number of output pixels line ------------------------------------------------------------- - number of input pixels line ---------------------------------------------------------- -------------------------------------------------------------- 4096 = yinc number of active output lines number of active input lines ---------------------------------------------------------------------------- 4096 = yiwgto yinc 2 ------------- - 2048 + = yiwgte yinc yskip C 2 ------------------------------------- - = 2004 mar 01 55 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 95 subaddresses a0h and a1h table 96 subaddress a1h table 97 subaddresses a2h to a4h table 98 subaddresses f0h to f2h table 99 subaddresses f3h to f5h table 100 subaddresses f6h to f8h table 101 subaddresses f9h and fah table 102 subaddress fah table 103 subaddresses fbh and fch data byte description yskip vertical line skip; de?nes the effectiveness of the anti-?icker ?lter; yskip = 0: most effective; yskip = 4095: anti-?icker ?lter switched off data byte logic level description blen 0 no internal blanking for non-interlaced graphics in bypass mode; default after reset 1 forced internal blanking for non-interlaced graphics in bypass mode data byte description bcy, bcu and bcv luminance and colour difference portion of border colour in underscan area data byte description cc1r, cc1g and cc1b red, green and blue portion of ?rst cursor colour data byte description cc2r, cc2g and cc2b red, green and blue portion of second cursor colour data byte description auxr, auxg and auxb red, green and blue portion of auxiliary cursor colour data byte description xcp horizontal cursor position data byte description xhs horizontal hot spot of cursor data byte description ycp vertical cursor position 2004 mar 01 56 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 table 104 subaddress fch table 105 subaddress fdh table 106 subaddress feh table 107 subaddress ffh in subaddresses 5bh, 5ch, 5dh, 5eh and 62h all ire values are rounded up. data byte description yhs vertical hot spot of cursor data byte logic level description lutoff 0 colour look-up table is active 1 colour look-up table is bypassed cmode 0 cursor mode; input colour will be inverted 1 auxiliary cursor colour will be inserted lutl 0 lut loading via input data stream is inactive 1 colour and cursor luts are loaded via input data stream if 0 input format is 8 + 8 + 8-bit 4 :4:4 non-interlaced rgb or c b -y-c r 1 input format is 5 + 5 + 5-bit 4 :4:4 non-interlaced rgb 2 input format is 5 + 6 + 5-bit 4 :4:4 non-interlaced rgb 3 input format is 8 + 8 + 8-bit 4 :2:2 non-interlaced c b -y-c r 4 input format is 8 + 8 + 8-bit 4 :2:2 interlaced c b -y-c r (itu-r bt.656, 27 mhz clock) (in subaddresses 91h and 94h set xpix = number of active pixels/line) 5 input format is 8-bit non-interlaced index colour 6 input format is 8 + 8 + 8-bit 4 :4:4 non-interlaced rgb or c b -y-c r (special bit ordering) matoff 0 rgb to c r -y-c b matrix is active 1 rgb to c r -y-c b matrix is bypassed dfoff 0 down formatter ( 4:4:4to4:2:2) in input path is active 1 down formatter is bypassed data byte description cursa ram start address for cursor bit map; the byte following subaddress feh points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition data byte description colsa ram start address for colour lut; the byte following subaddress ffh points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition 2004 mar 01 57 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 7.22 slave transmitter table 108 slave transmitter (slave address 89h) table 109 subaddress 00h table 110 subaddress 1ch table 111 subaddress 80h register function subaddress data byte d7 d6 d5 d4 d3 d2 d1 d0 status byte 00h ver2 ver1 ver0 ccrdo ccrde 0 fseq o_e chip id 1ch cid7 cid6 cid5 cid4 cid3 cid2 cid1 cid0 fifo status 80h 0 0 0 0 0 0 ovfl udfl data byte logic level description ver - version identi?cation of the device: it will be changed with all versions of the ic that have different programming models; current version is 010 binary ccrdo 1 closed caption bytes of the odd ?eld have been encoded 0 the bit is reset after information has been written to the subaddresses 67h and 68h; it is set immediately after the data has been encoded ccrde 1 closed caption bytes of the even ?eld have been encoded 0 the bit is reset after information has been written to the subaddresses 69h and 6ah; it is set immediately after the data has been encoded fseq 1 during ?rst ?eld of a sequence (repetition rate: ntsc = 4 ?elds, pal = 8 ?elds) 0 not ?rst ?eld of a sequence o_e 1 during even ?eld 0 during odd ?eld data byte description cid chip id of saa7102 = 02h; chip id of saa7103 = 03h data byte logic level description ovfl 0 no fifo over?ow 1 fifo over?ow has occurred; this bit is reset after this subaddress has been read udfl 0 no fifo under?ow 1 fifo under?ow has occurred; this bit is reset after this subaddress has been read 2004 mar 01 58 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 handbook, full pagewidth 6 8 10 12 14 6 0 024 mbe737 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) (1) (2) fig.4 chrominance transfer characteristic 1. (1) scbw = 1. (2) scbw = 0. handbook, halfpage 0 0.4 0.8 1.6 2 0 - 4 - 6 - 2 mbe735 1.2 f (mhz) g v (db) (1) (2) fig.5 chrominance transfer characteristic 2. (1) scbw = 1. (2) scbw = 0. 2004 mar 01 59 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 handbook, full pagewidth 6 (1) (2) (4) (3) 8101214 6 0 024 mgd672 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.6 luminance transfer characteristic 1 (excluding scaler). (1) ccrs1 = 0; ccrs0 = 1. (2) ccrs1 = 1; ccrs0 = 0. (3) ccrs1 = 1; ccrs0 = 1. (4) ccrs1 = 0; ccrs0 = 0. handbook, halfpage 02 (1) 6 1 0 - 1 - 2 - 3 - 4 - 5 mbe736 4 f (mhz) g v (db) fig.7 luminance transfer characteristic 2 (excluding scaler). (1) ccrs1 = 0; ccrs0 = 0. 2004 mar 01 60 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb708 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.8 luminance transfer characteristic in rgb (excluding scaler). handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb706 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.9 colour difference transfer characteristic in rgb (excluding scaler). 2004 mar 01 61 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 8 boundary scan test the saa7102; saa7103 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). the saa7102; saa7103 follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are test mode select (tms), test clock (tck), test reset ( trst), test data input (tdi) and test data output (tdo). the boundary scan test (bst) functions bypass, extest, intest, sample, clamp and idcode are all supported; see table 112. details about the jtag bst-test can be found in the specification ieee std. 1149.1 . a file containing the detailed boundary scan description language (bsdl) of the saa7102; saa7103 is available on request. table 112 bst instructions supported by the saa7102; saa7103 instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between tdi and tdo when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing when not all ics have bst. this instruction addresses the bypass register while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. intest this optional instruction allows testing of the internal logic (no support for customer available). user1 this private instruction allows testing by the manufacturer (no support for customer available). 8.1 initialization of boundary scan circuit the test access port (tap) controller of an ic should be in the reset state (test_logic_reset) when the ic is in functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting the trst pin low. 8.2 device identi?cation codes a device identification register is specified in ieee std. 1149.1b-1994 . it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and to determine the version number of the ics during field service. when the idcode instruction is loaded into the bst instruction register, the identification register will be connected between tdi and tdo of the ic. the identification register will load a component specific code during the capture_data_register state of the tap controller, this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to tdi) and bit 0 is the least significant bit (nearest to tdo); see fig.10. 2004 mar 01 62 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 handbook, full pagewidth 00000010101 0111000100000010 0010 4-bit version code 16-bit part number 11-bit manufacturer identification tdi tdo mhb909 31 msb lsb 28 27 12 11 1 0 1 handbook, full pagewidth 00000010101 0111000100000011 0010 4-bit version code 16-bit part number 11-bit manufacturer identification tdi tdo mhb910 31 msb lsb 28 27 12 11 1 0 1 fig.10 32 bits of identification code. b. saa7103. a. saa7102. 2004 mar 01 63 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 9 limiting values in accordance with the absolute maximum rating system (iec 60134); all ground pins connected together and grounded (0 v); all supply pins connected together. notes 1. condition for maximum voltage at digital inputs or i/o pins: 3.0 v < v ddd < 3.6 v. 2. class 2 according to eia/jesd22-114-b. 3. class a according to eia/jesd22-115-a. 10 thermal characteristics note 1. the overall r th(j-a) value can vary depending on the board layout. to minimize the effective r th(j-a) all power and ground pins must be connected to the power and ground layers directly. an ample copper area direct under the saa7102; saa7103 with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective r th(j-a) . please do not use any solder-stop varnish under the chip. in addition the usage of soldering glue with a high thermal conductance after curing is recommended. symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.5 +4.6 v v dda analog supply voltage - 0.5 +4.6 v v i(a) input voltage at analog inputs - 0.5 +4.6 v v i(n) input voltage at pins xtali, sda and scl - 0.5 v ddd + 0.5 v v i(d) input voltage at digital inputs or i/o pins outputs in 3-state - 0.5 +4.6 v outputs in 3-state; note 1 - 0.5 +5.5 v d v ss voltage difference between v ssa(n) and v ssd(n) - 100 mv t stg storage temperature - 65 +150 c t amb ambient temperature 0 70 c v esd electrostatic discharge voltage human body model; note 2 - 2000 v machine model; note 3 - 150 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air saa7102e 38 (1) k/w saa7103e 38 (1) k/w saa7102h 53 (1) k/w saa7103h 53 (1) k/w 2004 mar 01 64 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 11 characteristics v ddd = 3.0 to 3.6 v; t amb =0to70 c (typical values excluded); unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dda analog supply voltage 3.15 3.3 3.45 v v ddd digital supply voltage 3.0 3.3 3.6 v i dda analog supply current note 1 1 110 140 ma i ddd digital supply current note 2 1 70 90 ma inputs v il low-level input voltage at all digital input pins except pins sda and scl - 0.5 - +0.8 v v ih high-level input voltage at all digital input pins except pins sda and scl 2.0 - v ddd + 0.3 v i li input leakage current -- 10 m a c i input capacitance clocks -- 10 pf data -- 8pf i/os at high-impedance -- 8pf outputs; all digital output pins except pin sda v ol low-level output voltage i ol =2ma -- 0.4 v v oh high-level output voltage i oh = - 2 ma 2.4 -- v i 2 c-bus; pins sda and scl v il low-level input voltage - 0.5 - 0.3v ddd v v ih high-level input voltage 0.7v ddd - v ddd + 0.3 v i i input current v i = low or high - 10 - +10 m a v ol low-level output voltage (pin sda) i ol =3ma -- 0.4 v i o output current during acknowledge 3 -- ma clock timing; pins pixclki and pixclko t pixclk cycle time note 3 22.5 - 100 ns t d(clkd) delay from pixclko to pixclki note 4 --- ns d duty factor t high /t pixclk note 3 40 50 60 % duty factor t high /t clko2 output 40 50 60 % t r rise time note 3 -- 3ns t f fall time note 3 -- 3ns input timing t su;dat input data set-up time 5 -- ns t hd;dat input data hold time 0 -- ns crystal oscillator f nom nominal frequency - 27 - mhz d f/f nom permissible deviation of nominal frequency note 5 - 50 - +50 10 - 6 2004 mar 01 65 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 notes 1. minimum value for i 2 c-bus bit downa = 1. 2. minimum value for i 2 c-bus bit downd = 1. 3. the data is for both input and output direction. 4. this parameter is arbitrary, if pixclki is looped through the vgc. 5. if an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. c rystal specification t amb ambient temperature 0 - 70 c c l load capacitance 8 -- pf r s series resistance -- 80 w c 1 motional capacitance (typical) 1.2 1.5 1.8 ff c 0 parallel capacitance (typical) 2.8 3.5 4.2 pf data and reference signal output timing c o(l) output load capacitance 8 - 40 pf t o(h) output hold time 2 -- ns t o(d) output delay time -- 16 ns cvbs and rgb outputs v o(cvbs)(p-p) output voltage cvbs (peak-to-peak value) see table 113 - 1.23 - v v o(vbs)(p-p) output voltage vbs (s-video) (peak-to-peak value) see table 113 - 1.0 - v v o(c)(p-p) output voltage c (s-video) (peak-to-peak value) see table 113 - 0.89 - v v o(rgb)(p-p) output voltage r, g, b (peak-to-peak value) see table 113 - 0.7 - v d v o inequality of output signal voltages - 2 - % r o(l) output load resistance - 37.5 -w b dac output signal bandwidth of dacs - 3db 15 -- mhz ile lf(dac) low frequency integral linearity error of dacs -- 3 lsb dle lf(dac) low frequency differential linearity error of dacs -- 1 lsb symbol parameter conditions min. typ. max. unit 2004 mar 01 66 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 handbook, full pagewidth pixclko pixclki pdn any output t d(clkd) t high t f t r 2.4 v 1.5 v 0.4 v t hd;dat t hd;dat t o(h) t o(d) t su;dat t su;dat t pixclk mhb904 2.0 v 1.5 v 0.8 v 2.4 v 0.4 v 2.0 v 0.8 v fig.11 input/output timing specification. handbook, full pagewidth hsvgc pd cbo xofs idel xpix hlen mhb905 fig.12 horizontal input timing. 2004 mar 01 67 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 handbook, full pagewidth hsvgc vsvgc cbo yofs ypix mhb906 fig.13 vertical input timing. 2004 mar 01 68 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 11.1 teletext timing time t fd is the time needed to interpolate input data ttx and insert it into the cvbs and vbs output signal, such that it appears at t ttx = 9.78 m s (pal) or t ttx = 10.5 m s (ntsc) after the leading edge of the horizontal synchronization pulse. time t pd is the pipeline delay time introduced by the source that is gated by ttxrq_xclko2 in order to deliver ttx data. this delay is programmable by register ttxhd. for every active high state at output pin ttxrq_xclko2, a new teletext bit must be provided by the source. since the beginning of the pulses representing the ttxrq signal and the delay between the rising edge of ttxrq and valid teletext input data are fully programmable (ttxhs and ttxhd), the ttx data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse. time t i(ttxw) is the internally used insertion window for ttx data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 mbits/s (pal), 296 teletext bits at a text data rate of 5.7272 mbits/s (world standard ttx) or 288 teletext bits at a text data rate of 5.7272 mbits/s (nabts). the insertion window is not opened if the control bit ttxen is zero. using appropriate programming, all suitable lines of the odd field (ttxovs and ttxove) plus all suitable lines of the even field (ttxevs and ttxeve) can be used for teletext insertion. it is essential to note that the two pins used for teletext insertion must be configured for this purpose by the correct i 2 c-bus register settings . handbook, full pagewidth t i(ttxw) t ttx t pd t fd cvbs/y ttx_sres ttxrq_xclko2 text bit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mhb891 fig.14 teletext timing. 2004 mar 01 69 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 12 application information d book, full pagewidth mhb913 r12 75 w saa7102h saa7103h 16 17 18 19 44 43 42 41 pd3 pd2 pd1 pd0 22 pd7 pd [ 0:11 ] pd6 pd5 pd4 4 3 2 1 pd11 pd10 pd9 pd8 pd3 pd2 pd1 pd0 pd7 pd6 pd5 pd4 pd11 pd10 pd9 pd8 v dda3_2 v dda3_1 v dd3_2 v dd3_1 v ddd2 v ddd1 v dda2 v dda1 tms tdi tdo bst0 bst1 bst2 tck trst sda scl hsvgc hsvgc 34 35 xtalo xtali 14 vsvgc vsvgc 13 fsvgc fsvgc 21 cbo tp5 hsvgc tp4 cbo tp3 xclko2 cbo 23 ttx_sres ttx_sres 24 ttxrq_ xclko2 ttxrq_xclko2 v ssd2 v ssd1 dump rset pixclki pixclko reset v ssa1 agnd dgnd dgnd 10 40 36 29 6 38 7 8 37 11 12 26 hsm_csync hsm_csync 25 vsm vsm 27 28 30 fltr0 fltr1 fltr2 bst [ 0:2 ] tdi tdo scl sda fltr [ 0:2 ] red_cr_c green_vbs_cvbs blue_cb_cvbs y1 27 mhz c7 10 pf c8 10 pf c9 1 nf 10 m h l1 33 9 39 32 31 15 20 5 r3 0 w v dda3_1 v dd3_1 v dda3_2 v dd3_2 c1 100 nf dgnd agnd c4 100 nf c2 100 nf c3 100 nf r9 12 w agnd agnd r8 1 k w r7 22 w r6 22 w jp9 reset jp10 clk short cp1 22 m f reset pixclko pixclki reset s1 v dd3_0 r2 4.7 k w dgnd r11 75 w agnd r10 75 w agnd fig.15 application circuit. 2004 mar 01 70 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 handbook, halfpage mhb912 2.7 m h 120 pf c16 jp11 jp12 fin fout c10 390 pf c13 560 pf l2 2.7 m h l3 filter 1 = byp. ll act. agnd fig.16 fltr0, fltr1 and fltr2 of fig.15. 12.1 analog output voltages the analog output voltages are dependent on the total load (typical value 37.5 w ), the digital gain parameters and the i 2 c-bus settings of the dac reference currents (analog settings). the digital output signals in front of the dacs under nominal (nominal here stands for the settings given in tables 54 to 61 for example a standard pal or ntsc signal) conditions occupy different conversion ranges, as indicated in table 113 for a 100 100 colour bar signal. by setting the reference currents of the dacs as shown in table 113, standard compliant amplitudes can be achieved for all signal combinations; it is assumed that in subaddress 16h, parameter dacf = 0000b, that means the fine adjustment for all dacs in common is set to 0%. if s-video output is desired, the adjustment for the c (chrominance subcarrier) output should be identical to the one for vbs (luminance plus sync) output. table 113 digital output signals conversion range set/out cvbs, sync tip-to-white vbs, sync tip-to-white rgb, black-to-white digital settings see tables 54 to 61 see tables 54 to 61 see table 49 digital output 1014 881 876 analog settings e.g. b dac = 1fh e.g. g dac = 1bh e.g. r dac = g dac = b dac = 0bh analog output 1.23 v (p-p) 1.00 v (p-p) 0.70 v (p-p) 12.2 suggestions for a board layout use separate ground planes for analog and digital ground. connect these planes only at one point directly under the device, by using a 0 w resistor directly at the supply stage. use separate supply lines for the analog and digital supply. place the supply decoupling capacitors close to the supply pins. use l bead (ferrite coil) in each digital supply line close to the decoupling capacitors to minimize radiation energy (emc). place the analog coupling (clamp) capacitors close to the analog input pins. place the analog termination resistors close to the coupling capacitors. be careful of hidden layout capacitors around the crystal application. use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects and to soften data energy. 2004 mar 01 71 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 13 package outlines 1 a a 1 e 1 b a 2 a 1 a 2 detail x y unit d y e references outline version european projection issue date 00-03-04 03-01-22 iec jedec jeita mm 0.5 0.3 1.75 15.2 14.8 d 1 13.7 13.0 13.7 13.0 e 1 13 e 2 13 1.25 1.05 y 1 0.6 0.4 0.1 0.15 0.35 dimensions (mm are the original dimensions) sot472-1 144e ms-034 - - - 15.2 14.8 ew 0.3 v 05 10 mm scale sot472-1 bga156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm a max. y 1 c c e 1 d d 1 x e 1 a b c d e f g h j k l m n p 234567891011121314 b a ball a1 index area e e e 1 b e 2 a c c b ? v m ? w m shape optional (4x) 1/2 e 1/2 e 2004 mar 01 72 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 97-08-01 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.1 2004 mar 01 73 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 14 soldering 14.1 introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. 14.2 through-hole mount packages 14.2.1 s oldering by dipping or by solder wave typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.2.2 m anual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 14.3 surface mount packages 14.3.1 r eflow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all the bga, htsson..t and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3.2 w ave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. 2004 mar 01 74 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.3.3 m anual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2004 mar 01 75 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 14.4 suitability of ic packages for wave, re?ow and dipping soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 4. hot bar soldering or manual soldering is suitable for pmfp packages. 5. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 6. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 7. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 8. wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 9. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 10. hot bar or manual soldering is suitable for pmfp packages. 11. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. mounting package (1) soldering method wave reflow (2) dipping through-hole mount cpga, hcpga suitable - suitable dbs, dip, hdip, rdbs, sdip, sil suitable (3) -- through-hole- surface mount pmfp (4) not suitable not suitable - surface mount bga, htsson..t (5) , lbga, lfbga, sqfp, ssop-t (5) , tfbga, uson, vfbga not suitable suitable - dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (6) suitable - plcc (7) , so, soj suitable suitable - lqfp, qfp, tqfp not recommended (7)(8) suitable - ssop, tssop, vso, vssop not recommended (9) suitable - cwqccn..l (11) , pmfp (10) , wqccn32l (11) not suitable not suitable - 2004 mar 01 76 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 15 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 16 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 mar 01 77 philips semiconductors product speci?cation digital video encoder saa7102; saa7103 18 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. ? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r21/03/pp78 date of release: 2004 mar 01 document order number: 9397 750 11445 |
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